processor_7tdmi.cpp

浙江大学的悟空嵌入式系统模拟器

/*
*  Copyright (c) 2005 Zhejiang University, P.R.China
*
*  This program is free software; you can redistribute it and/or modify
*  it under the terms of the GNU General Public License as published by
*  the Free Software Foundation; either version 2 of the License, or
*  (at your option) any later version.
*
*  This program is distributed in the hope that it will be useful,
*  but WITHOUT ANY WARRANTY; without even the implied warranty of
*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*  GNU General Public License for more details.
*
*  You should have received a copy of the GNU General Public License
*  along with this program; if not, write to the Free Software
*  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ 

//=============================================================================
/**
*  \file    Arch/ARM/Processor_7TDMI.h
*
*  $Id: Processor_7TDMI.cpp,v 1.12 2005/06/08 07:40:46 qilj Exp $
*
*  \author  zhao jun <[e-mail]>
*/
//=============================================================================

#include "./Processor_7TDMI.h"

#include "Core/Memory.h"
#include "./Board_AT91EV40.h"
#include "Compare.h"
#include "MMU.h"

namespace ARM{

	CPU_7TDMI::CPU_7TDMI(Core::Instruction_Set & instr_set, Core::MMU<Core::u32> * mmu)
		: ARM::ARM_CPU(instr_set, mmu)
	{
		//set pc 
	}

	void CPU_7TDMI::on_create()
	{
		config_.name = "ARM7TDMI";
		config_.family = "ARMv4";
		load_register();
		ARM_CPU::on_create();
		install_coprocessor();
	}

	void CPU_7TDMI::on_reset()
	{
		current_bpt_.addr = -1;
		current_mode_ = Svc;
		set_cpsr(0xd3);
		write_register(R1, 91);
		//for debug
		con_ = false;
	}

	void CPU_7TDMI::on_reset_exception()
	{
		current_mode_ = ARM_CPU::Svc;
		Core::Register_Int val;
		read_register(ARM_CPU::CPSR, val);

		val = val & BINARY32(1111, 1111, 1111, 1111, 1111, 1111, 1101, 0011);
		val = val | BINARY32(0000, 0000, 0000, 0000, 0000, 0000, 1101, 0011);
		set_cpsr(val);
#ifdef	HIGH_VECTORS
		set_pc(Core::u32(0xffff0000));
#else
		set_pc(Core::u32(0x00000000));
#endif
	}

	void CPU_7TDMI::on_undefined_instruction()
	{
		current_mode_ = ARM_CPU::Und;
		write_register(ARM_CPU::R14_und, (Core::Register_Int)get_pc());
		Core::Register_Int val;
		read_register(ARM_CPU::CPSR, val);
		write_register(ARM_CPU::SPSR_und, val);

		val = val & BINARY32(1111, 1111, 1111, 1111, 1111, 1111, 1101, 1011);
		val = val | BINARY32(0000, 0000, 0000, 0000, 0000, 0000, 1001, 1011);
		set_cpsr(val);

#ifdef	HIGH_VECTORS
		set_pc(Core::u32(0xffff0004));
#else
		set_pc(Core::u32(0x00000004));
#endif

		push_expception(ARM_CPU::Undef_exp);
	}

	void CPU_7TDMI::on_prefetch_exception()
	{
		current_mode_ = ARM_CPU::Abt;
		write_register(ARM_CPU::R14, (Core::Register_Int)(get_pc())+4);
		Core::Register_Int val;
		val = get_cpsr().convert_to_int();
		get_spsr().convert_from_int(val);

		val = val & BINARY32(1111, 1111, 1111, 1111, 1111, 1111, 1101, 0111);
		val = val | BINARY32(0000, 0000, 0000, 0000, 0000, 0000, 1001, 0111);
		set_cpsr(val);

			set_pc(Core::u32(0x0000000c));

		push_expception(ARM_CPU::PreAbt_exp);
	}

	void CPU_7TDMI::on_dataabt_exception()
	{
		current_mode_ = ARM_CPU::Abt;
		write_register(ARM_CPU::R14, (Core::Register_Int)(get_pc())+4);
		Core::Register_Int val;
		val = get_cpsr().convert_to_int();
		get_spsr().convert_from_int(val);

		val = val & BINARY32(1111, 1111, 1111, 1111, 1111, 1111, 1101, 0111);
		val = val | BINARY32(0000, 0000, 0000, 0000, 0000, 0000, 1001, 0111);
		set_cpsr(val);

				set_pc(Core::u32(0x00000010));

		push_expception(ARM_CPU::DataAbt_exp);
	}

	void CPU_7TDMI::on_irq_exception()
	{
		current_mode_ = ARM_CPU::IRQ;
		write_register(ARM_CPU::R14, (Core::Register_Int)(get_pc()+4));
		Core::Register_Int val;
		val = get_cpsr().convert_to_int();
		get_spsr().convert_from_int(val);

		val = val & BINARY32(1111, 1111, 1111, 1111, 1111, 1111, 1101, 0010);
		val = val | BINARY32(0000, 0000, 0000, 0000, 0000, 0000, 1001, 0010);
		set_cpsr(val);

			set_pc(Core::u32(0x00000018)); 

		push_expception(ARM_CPU::IRQ_exp);
	}

	void CPU_7TDMI::on_fiq_exception()
	{
		current_mode_ = ARM_CPU::FIQ;
		write_register(ARM_CPU::R14_fiq, (Core::Register_Int)(get_pc()+4));
		Core::Register_Int val;
		read_register(ARM_CPU::CPSR, val);
		write_register(ARM_CPU::SPSR_fiq, val);

		val = val & BINARY32(1111, 1111, 1111, 1111, 1111, 1111, 1101, 0001);
		val = val | BINARY32(0000, 0000, 0000, 0000, 0000, 0000, 1101, 0001);
		set_cpsr(val);

#ifdef HIGH_VECTORS
		set_pc(Core::u32(0xffff001c));
#else
		set_pc(Core::u32(0x0000001c));
#endif

		push_expception(ARM_CPU::FIQ_exp);
	}

	void CPU_7TDMI::on_swi_exception()
	{
		current_mode_ = ARM_CPU::Svc;
		write_register(ARM_CPU::R14, (Core::Register_Int)(get_pc()));

		Core::Register_Int val;
		val = get_cpsr().convert_to_int();
		get_spsr().convert_from_int(val);

		val = val & BINARY32(1111, 1111, 1111, 1111, 1111, 1111, 1101, 0011);
		val = val | BINARY32(0000, 0000, 0000, 0000, 0000, 0000, 1001, 0011);
		set_cpsr(val);

			set_pc(Core::u32(0x00000008)); 

		push_expception(ARM_CPU::SWI_exp);
	}

}