📄 coprocessor.h
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/*
* Copyright (c) 2005 Zhejiang University, P.R.China
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
//=============================================================================
/**
* \file ARM/MMU.h
*
* $Id: Coprocessor.h,v 1.5 2005/06/15 12:50:42 jiajc Exp $
*
* \author Juncheng Jia <jiajuncheng@gmail.com>
*/
//=============================================================================
#ifndef ARM__COPROCESSOR_H_INCLUDED
#define ARM__COPROCESSOR_H_INCLUDED
#include "Core/Processor.h"
namespace ARM{
//! ARM Coprocessor
class ARM_Coprocessor : public Core::Coprocessor
{
public:
//! Execution of coprocessor instructions
virtual void STC(Core::Instruction_Unit binary) { WUKONG_STDOUT << "Undefined Copro Instr stc" <<std::endl; }
virtual void LDC(Core::Instruction_Unit binary) { WUKONG_STDOUT << "Undefined Copro Instr ldc" <<std::endl; }
virtual void CDP(Core::Instruction_Unit binary) { WUKONG_STDOUT << "Undefined Copro Instr cdp" <<std::endl; }
virtual void MCR(Core::Instruction_Unit binary) { WUKONG_STDOUT << "Undefined Copro Instr mcr" <<std::endl; }
virtual void MRC(Core::Instruction_Unit binary) { WUKONG_STDOUT << "Undefined Copro Instr mrc" <<std::endl; }
virtual void MAR(Core::Instruction_Unit binary) { WUKONG_STDOUT << "Undefined Copro Instr mar" <<std::endl; }
virtual void MRA(Core::Instruction_Unit binary) { WUKONG_STDOUT << "Undefined Copro Instr mra" <<std::endl; }
};
//! CP15 ( System Control Coprocessor )
class CP15 : public ARM_Coprocessor
{
public:
//! Registers of CP15
enum{
ID_CODE = 0, // 0
CACHE_TYPE, // 0
CONTROL, // 1
TRANSLATION_TABLE_BASE, // 2
DOMAIN, // 3
// 4
FAULT_STATUS, // 5
FAULT_ADDRESS, // 6
CACHE_FUNCTIONS, // 7
TLB_FUNCTIONS, // 8
CACHE_LOCKDOWN, // 9
TLB_LOCKDOWN, // 10
// 11
// 12
PROCESS_ID, // 13
BREAKPOINT, // 14
COPROCESSOR_ACCESS // 15
} Reg_Num;
// Bit of register #1 ( Control register )
enum
{
CONTROL_MMU = (1<<0),
CONTROL_ALIGN_FAULT = (1<<1),
CONTROL_CACHE = (1<<2),
CONTROL_DATA_CACHE = (1<<2),
CONTROL_WRITE_BUFFER = (1<<3),
CONTROL_BIG_ENDIAN = (1<<7),
CONTROL_SYSTEM = (1<<8),
CONTROL_ROM = (1<<9),
CONTROL_UNDEFINED = (1<<10),
CONTROL_BRANCH_PREDICT= (1<<11),
CONTROL_INSTRUCTION_CACHE = (1<<12),
CONTROL_VECTOR = (1<<13),
CONTROL_RR = (1<<14),
CONTROL_L4 = (1<<15)
};
//! Ctor
CP15(Core::u32 id);
//! Dtor
virtual ~CP15(void) = 0;
//! Test if "high vectors" is used
bool is_high_vectors();
protected:
static const std::string reg_name_[17];
Core::u32 id_code_;
};
//! CP14
class CP14 : public ARM_Coprocessor
{
public:
//! Register
enum {
PMNC, //0
CCNT, //1
PMN0, //2
PMN1, //3
CCLKCFG, //6
PWRMODE, //7
} Reg_Num;
virtual void MCR(Core::Instruction_Unit binary);
virtual void MRC(Core::Instruction_Unit binary);
virtual void LDC(Core::Instruction_Unit binary);
virtual void STC(Core::Instruction_Unit binary);
virtual void on_create() {}
virtual void on_reset() {}
virtual void on_destroy() {}
protected:
Core::u32 cclkcfg_; //!< CCLKCFG Register
Core::u32 pwrmode_; //!< PWRMODE Register
};
//! CP0
class CP0 : public ARM_Coprocessor
{
public:
virtual void MAR(Core::Instruction_Unit binary) ;
virtual void MRA(Core::Instruction_Unit binary) ;
virtual void on_create() {}
virtual void on_reset() {}
virtual void on_destroy() {}
protected:
Core::u8 hi_; //!< 8 high bits
Core::u32 lo_; //!< 32 low bits
};
}// namespace
#endif
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