📄 board_pxa_lubbock.cpp
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ostimer_reg_[OSCR] = target;
break;
case 0x40A00000: //OSMR0
ostimer_reg_[OSMR0] = target;
break;
case 0x40A00004: //OSMR1
ostimer_reg_[OSMR1] = target;
break;
case 0x40A00008: //OSMR2
ostimer_reg_[OSMR2] = target;
break;
case 0x40A0000C: //OSMR3
ostimer_reg_[OSMR3] = target;
break;
case 0x40A00018: //OWER
ostimer_reg_[OWER] |= target & 0x1;
break;
case 0x40A00014: //OSSR
ostimer_reg_[OSSR] &= ~(target & 0xf);
break;
case 0x40A0001C: //OIER
ostimer_reg_[OIER] = target & 0xf;
break;
case 0x40D00004: //ICMR
ic_reg_[ICMR] = target;
break;
case 0x40D00008: //ICLR
ic_reg_[ICLR] = target;
break;
//ffuart contril
case 0x40100000: //FFTHR
case 0x40100004: //FFIER
case 0x40100008: //FFFCR //write only
case 0x4010000C: //FFLCR
uart_->on_mapped_memory_write(start, size, buffer);
break;
//Clocks Manager Register
case 0x41300000: //CCCR
cm_reg_[CCCR] = target & 0x3ff;
break;
case 0x41300004: //CKEN
cm_reg_[CKEN] = target & 0x17def;
break;
case 0x41300008: //OSCC
cm_reg_[OSCC] = target & 0x3;
break;
default:
return Core::Dummy_MMU<Core::u32>::MEMORY_IO_RW;
}
}
else
{
return Core::Dummy_MMU<Core::u32>::MEMORY_IO_RW;
}
return Core::Dummy_MMU<Core::u32>::MEMORY_SUCCESSFUL;
}
void Board_PXA_Lubbock::io_do_cycle(void)
{
descend_io_prescale();
if(test_io_prescale())
{
reset_io_prescale();
if(is_kb_input())
{
is_kb_input_ = true;
char buf;
Core::u32 & FFRBR = ((DEVICE::FFUART *)uart_)->get_FFRBR();
Core::u32 & FFIIR = ((DEVICE::FFUART *)uart_)->get_FFIIR();
Core::u32 & FFLSR = ((DEVICE::FFUART *)uart_)->get_FFLSR();
Core::s32 n = kb_read(0, &buf, 1);
if (n)
{
FFRBR = (int)buf;
FFIIR |= 0x4; //Rx idle
FFLSR |= 0x01; //Data ready
Core::u32 & i = ((DEVICE::FFUART *)uart_)->get_FFRBR();
}
}
}
}
Core::Interrupt_Type Board_PXA_Lubbock::get_highest_interrupt(void)
{
descend_rt_clock();
descend_os_clock();
if(is_kb_input_)
{
is_kb_input_ = false;
return Board_PXA_Lubbock::UXINT_INT;
}
else if( rt_scale == 0 )
{
reset_rt_clock();
return Board_PXA_Lubbock::RT_CLOCK_INT;
}
else if(os_scale == 0)
{
reset_os_clock();
return Board_PXA_Lubbock::OS_CLOCK_INT;
}
else
{
//clock--;
//set_signal(Board_PXA_Lubbock::IRQ_sig, false);
return Inter_Undefined;
}
}
void Board_PXA_Lubbock::on_interrupt(Core::Interrupt_Type type)
{
Core::u32 mask;
Core::u32 count;
switch(type)
{
case Board_PXA_Lubbock::RT_CLOCK_INT:
/*RTC*/
if (rt_count ++ == (rtc_reg_[RTTR] & 0xffff)){
rt_count = 0;
//Following each rising edge of the HZ clock, RTAR is compared to the RCNR.
if (rtc_reg_[RCNR]++ == rtc_reg_[RTAR])
{
if (rtc_reg_[RTSR] & 0x4)
{
//An RTC alarm has been detected (RTNR matches RCAR) and ALE bit is set
rtc_reg_[RTSR] |= 0x1;
}
}
if (rtc_reg_[RTSR] & 0x8)
{
//A rising edge has been detected and HZE bit is set.
rtc_reg_[RTSR] |= 0x2;
}
}
break;
case Board_PXA_Lubbock::OS_CLOCK_INT:
mask=0;
count = ostimer_reg_[OSCR]++;
if (count == ostimer_reg_[OSMR0])
mask = 1;
if (count == ostimer_reg_[OSMR1])
mask |= 0x2;
if (count == ostimer_reg_[OSMR2])
mask |= 0x4;
if (count == ostimer_reg_[OSMR3])
mask |= 0x8;
ostimer_reg_[OSSR] |= mask;
break;
case Board_PXA_Lubbock::UXINT_INT:
break;
default:
// signal_[IRQ_sig] = false;
break;
}
set_external_interrupt();
}
void Board_PXA_Lubbock::poll_extern_exception()
{
Core::Register &cpsr = cpu_->get_cpsr();
CPU_XScale::CPU_Interrupt current_exp_priority = cpu_->get_exp_priority();
if(current_exp_priority > 3 || current_exp_priority < 0)
{
if( test_signal(Board_PXA_Lubbock::FIQ_sig) \
&& !cpsr.test(6) )
{
cpu_->do_exception(CPU_XScale::FIQ_exp);
set_signal(Board_PXA_Lubbock::FIQ_sig, false);
}
}
if(current_exp_priority > 4 || current_exp_priority < 0)
{
if( test_signal(Board_PXA_Lubbock::IRQ_sig) \
&& !cpsr.test(7) )
{
cpu_->do_exception(CPU_XScale::IRQ_exp);
set_signal(Board_PXA_Lubbock::IRQ_sig, false);
}
}
}
void Board_PXA_Lubbock::set_external_interrupt()
{
Core::u32 irq = 0;
Core::u32 mask;
// RTC
if ((rtc_reg_[RTSR] & 0x1) && (rtc_reg_[RTSR] & 0x4))
irq |= RTC_ALARM_IRQ;
if ((rtc_reg_[RTSR] & 0x2) && (rtc_reg_[RTSR] & 0x8))
irq |= RTC_HZ_IRQ;
// OS time
mask = ostimer_reg_[OIER] & ostimer_reg_[OSSR];
irq |= (mask << OS_IRQ_SHF);
Core::u32 & FFIER = ((DEVICE::FFUART *)uart_)->get_FFIER();
Core::u32 & FFIIR = ((DEVICE::FFUART *)uart_)->get_FFIIR();
Core::u32 & FFLSR = ((DEVICE::FFUART *)uart_)->get_FFLSR();
if((FFIER & 0x1) && (FFIIR & 0x4)){
irq |= FFUART_IRQ;
FFIIR &=~0x1;
}
if (FFIER & 0x2){
irq |= FFUART_IRQ;
FFIIR |=0x2;
FFIIR &=~0x1;
FFLSR |=0x60;
}
ic_reg_[ICPR] = irq;
ic_reg_[ICIP] = (ic_reg_[ICMR] & ic_reg_[ICPR]) & ~ic_reg_[ICLR];
if( ic_reg_[ICIP])
set_signal(Board_PXA_Lubbock::IRQ_sig, true);
else
set_signal(Board_PXA_Lubbock::IRQ_sig, false);
}
#ifdef LINUX
Core::s32 Board_PXA_Lubbock::kb_input()
{
fd_set rfds;
struct timeval tv;
FD_ZERO(&rfds);
FD_SET(0, &rfds);
tv.tv_sec = 0;
tv.tv_usec = 0;
return select(0+1, &rfds, NULL, NULL, &tv) ;
}
#endif
#ifdef WIN32
Core::s32 Board_PXA_Lubbock::kb_read(Core::s32 fd,char *buffer, Core::s32 count)
{
size_t size = Core::Wukong_Get_System().get_key_event_count();
if (size == 0)
return 0;
for (size_t i = 0; (i < size) &&( i < count); ++i)
{
Core::System::Key_Event evt = Core::Wukong_Get_System().top_key_event();
Core::Wukong_Get_System().pop_key_event();
buffer[i] = (char)evt.keycode;
if( buffer[i] == '\r')
buffer[i] = '\n';
}
return i;
/*Core::u32 i;
for( i = 0; (i< count) && kbhit(); i++)
{
// WUKONG_STDOUT<<"_"<<std::endl;
buffer[i] = getch();
//buffer[i] = fgetc(stdin);
if( buffer[i] == '\r')
buffer[i] = '\n';
}
return i;*/
}
#endif
}
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