arm_processor.h

浙江大学的悟空嵌入式系统模拟器

/*
*  Copyright (c) 2005 Zhejiang University, P.R.China
*
*  This program is free software; you can redistribute it and/or modify
*  it under the terms of the GNU General Public License as published by
*  the Free Software Foundation; either version 2 of the License, or
*  (at your option) any later version.
*
*  This program is distributed in the hope that it will be useful,
*  but WITHOUT ANY WARRANTY; without even the implied warranty of
*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*  GNU General Public License for more details.
*
*  You should have received a copy of the GNU General Public License
*  along with this program; if not, write to the Free Software
*  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ 

//=============================================================================
/**
*  \file    Arch/ARM/ARM_Processor.h
*
*  $Id: ARM_Processor.h,v 1.2 2005/06/16 11:24:50 qilj Exp $
*
*  \author  Lingjie Qi <[e-mail]> 
*/
//=============================================================================
#ifndef ARM__PROCESSOR_H_INCLUDED
#define ARM__PROCESSOR_H_INCLUDED

#include "Processor.h"
#include "Global.h"
#include "Datatype.h"
#include "HelperMacro.h"
#include "Log.h"
#include "Coprocessor.h"

class Core::Board;
class Core::Debugger;

#include <stack>

namespace ARM{
	class Instruction_Set;

	class MMU;

	class ARM_Coprocessor;

	class ARM_CPU : public Core::CPU_32Bit
	{
	public:

		//! registers' index
		enum {
			R0 = 0, R1,  R2,  R3,
			R4,     R5,  R6,  R7,
			R8,     R9,  R10, R11,    
			R12,    R13, R14, R15, pc = 15,
			R8_fiq = 16, R9_fiq,  R10_fiq,
			R11_fiq,     R12_fiq, R13_fiq,
			R14_fiq,
			R13_irq = 23,  R14_irq,
			R13_svc = 25,  R14_svc,
			R13_abt = 27,  R14_abt,
			R13_und = 29,  R14_und,
			CPSR,
			SPSR_svc,  SPSR_abt,
			SPSR_und,  SPSR_irq, SPSR_fiq,
			REG_END = 37
		}Register;

		//! cpu's mode
		typedef enum {
			User = BINARY4(0000), FIQ = BINARY4(0001),
			IRQ  = BINARY4(0010), Svc = BINARY4(0011),
			Abt = BINARY4(0111),  Und = BINARY4(1011),
			Sys = BINARY4(1111)
		}CPU_Mode;

		//! cpu's interrupt
		typedef enum{
			Rst_exp = 1,
			Undef_exp = 6,
			PreAbt_exp = 5,
			DataAbt_exp = 2,
			IRQ_exp = 4,
			FIQ_exp = 3,
			SWI_exp = 7,
			NO_exp = -1
		}CPU_Interrupt;

		//!BreakPoint is used when it is runned as GDB target 
		struct BreakPoint{
			Core::u32 addr;
			Core::Bytecode_Type res;   //the real instruciont
			bool is_break;
			Core::Debugger::Breakpoint_Type btype;
		};

		//!Constructor
		ARM_CPU(Core::Instruction_Set & instr_set, Core::MMU<Core::u32> * mmu);

		virtual ~ARM_CPU(void){}

		//!check current interruption
		virtual void on_interrupt(Core::Interrupt_Type type){}

		//! fetch the instruction from memory 
		virtual Core::Instruction_Unit fetch_instruction(Core::u32 pc);

		//! run loop, overwrite the run function of base class
		virtual void run(void);

		//!debugging_run  is used when it is runned as GDB target 
		virtual void debugging_run();

		//!prefectch exception
		virtual void on_prefetch_exception(void){}

		//!memory exception
		virtual void on_memory_exception(void){}

		//!no use
		virtual void on_undefined_instruction(Core::Instruction_Unit binary) {}

		//!undefined instruction exception
		virtual void on_undefined_instruction(void){}

		//!reset exception
		virtual void on_reset_exception(void){}

		//!data abort exception
		virtual void on_dataabt_exception(void){}

		//!IRQ exception
		virtual void on_irq_exception(void){}

		//!FIQ exception
		virtual void on_fiq_exception(void){}

		//!swi exception
		virtual void on_swi_exception(void){}

		//!when the cpu is created , it is called
		virtual void on_create(void);

		//!when the cpu is destroyed, it is called
		virtual void on_destroy(void){}

		//!when the cpu is created , it is called
		virtual void on_reset(void){}

		//! overwrite the function of base class 
		virtual bool read_register(size_t idx, Core::Register_Int & val);

		//! read register of user-mode
		bool read_user_register(size_t idx, Core::Register_Int & val);

		//! overwrite the function of base class
		virtual bool write_register(size_t idx, Core::Register_Int val);

		//! write register of user-mode
		bool write_user_register(size_t idx, Core::Register_Int val);

		//! configure registers in cpu
		void load_register();

		//! get current mode of cpu 
		CPU_Mode get_cpu_mode();

		//! set cpu's mode 
		void set_cpu_mode();

		//! do checking cpu's mode and change the cpu's mode when the mode is changed
		//CPU_Mode check_mode();

		//! adjust register's index depend on cpu's mode
		void adjust_reg_idx(size_t &idx);

		//! return spsr register depend on cpu mode
		Core::Register & get_spsr();

		//! return cpsr register
		Core::Register & get_cpsr();

		//! pop up the exception
		CPU_Interrupt pop_exception();

		//! push the generant exception
		void push_expception(CPU_Interrupt exp);

		//! set the current exception's priority
		void set_exp_priority(CPU_Interrupt pri);

		//! get the current exception's priority
		CPU_Interrupt get_exp_priority();

		//! process processor's interrupts
		void do_exception(CPU_Interrupt exp);

		//! poll extern interrupts
		//void poll_extern_exception(Core::Board<Core::u32> *board);

		//! set cpsr register's value
		void set_cpsr(Core::u32 val);

		//! set shifter_carry_out
		void set_shifter_carry_out(Core::u8 val);

		//! get the value of shifter_carry_out
		Core::u8 get_shifter_carry_out();

		//! set pc value
		virtual bool set_pc(Core::Register_Int val);

		//! get pc value
		virtual Core::Register_Int get_pc();

		//! install coprocessor
		virtual void install_coprocessor(void){}
		
		ARM_Coprocessor * get_coprocessor(size_t index);

		//! insert breakpoint
		Core::s32 insert_breakpoint(Core::Debugger::Breakpoint_Type btype,Core::u32 addr, size_t len);

		//! remove breakpoint
		Core::s32 remove_breakpoint(Core::Debugger::Breakpoint_Type btype,Core::u32 addr, size_t len);

		//! get the pc which is pointing current instruction
		Core::u32 get_factual_pc();

		//! get the current breakpoint 
		BreakPoint & get_current_bpt();

		//! find the breakpoint whose address is addr
		BreakPoint & find_bpt(Core::u32 addr);

		//! step info
		virtual void step_info();
		
		//! step over
		virtual void step_over();

		//! continue
		virtual void con();

	protected:

		Core::Processor::Config config_;
		static std::string reg_name_[(Core::u32)ARM_CPU::REG_END];
		CPU_Mode current_mode_;
		std::stack<CPU_Interrupt> exp_priority_;
		CPU_Interrupt	current_exp_priority_;
		Core::u8 shifter_carry_out_;

		//! for debug info
		std::map<Core::u32, BreakPoint> bpt_map_;
		BreakPoint current_bpt_;
		Core::u32 factual_pc_;
		bool con_;

	};

#include "ARM_Processor_i.h"
}
#endif