mmu_i.h

浙江大学的悟空嵌入式系统模拟器

/*
 *  Copyright (c) 2005 Zhejiang University, P.R.China
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */ 

//=============================================================================
/**
 *  @file    ARM/MMU_i.h
 *
 *  $Id: MMU_i.h,v 1.3 2005/06/15 12:50:42 jiajc Exp $
 *
 *  @author  Juncheng Jia <[e-mail]>
 */
//=============================================================================

inline u32 TLB::get_pa(TLB::Entry *entry, u32 va)
{
	return (entry->pa & masks [entry->mapping]) |
		(va & ~masks[entry->mapping]);
}

inline u32 Cache::get_tag(u32 va)
{
	return va & ~(num_width_ - 1);
}

inline size_t Cache::get_set_index(u32 va)
{
	return (va / num_width_) & (num_set_ - 1);
}

inline size_t Cache::get_width()
{
	return num_width_;
}

inline size_t Cache::get_way()
{
	return num_way_;
}

inline size_t Cache::get_set()
{
	return num_set_;
}

inline CP15 * MMU::get_cp15()
{
	return (CP15 *)(get_cpu()->get_coprocessor(15));
}

inline ARM_CPU * MMU::get_cpu()
{
	return (ARM_CPU *)Core::Wukong_Get_System().get_cpu(0);
}

inline bool MMU::is_enable()
{
	u32 value;
	get_cp15()->read_register(CP15::CONTROL, value);
	return ( value & CP15::CONTROL_MMU ) ? true : false;
}

inline void MMU::enable()
{
	u32 value;
	get_cp15()->read_register(CP15::CONTROL, value);
	value |= CP15::CONTROL_MMU;
	get_cp15()->write_register(CP15::CONTROL, value);
}

inline void MMU::disable()
{
	u32 value;
	get_cp15()->read_register(CP15::CONTROL, value);
	value &= ~CP15::CONTROL_MMU;
	get_cp15()->write_register(CP15::CONTROL, value);
}

inline bool MMU::system_protection_on()
{
	u32 value;
	get_cp15()->read_register(CP15::CONTROL, value);
	return ( value & CP15::CONTROL_SYSTEM ) ? true : false;
}

inline bool MMU::rom_protection_on()
{
	u32 value;
	get_cp15()->read_register(CP15::CONTROL, value);
	return ( value & CP15::CONTROL_ROM ) ? true : false;
}

inline bool MMU::is_user_mode()
{
	return get_cpu()->get_cpu_mode() == ARM_CPU::User;
}

inline TLB::Domain_Access_Type MMU::domain_access_type(u32 domain_num)
{
	u32 value;
	get_cp15()->read_register(CP15::DOMAIN, value);
	return (TLB::Domain_Access_Type)((value >> (domain_num * 2)) & 3);
}

inline void MMU::set_fault_status(u32 value)
{
	get_cp15()->write_register(CP15::FAULT_STATUS,value);
}

inline void MMU::set_fault_address(u32 value)
{
	get_cp15()->write_register(CP15::FAULT_ADDRESS, value);
}

inline u32 MMU::get_translation_table_base()
{
	u32 value;
	get_cp15()->read_register(CP15::TRANSLATION_TABLE_BASE, value);
	return value;
}

inline bool MMU::align_fault_check_on()
{
	u32 value;
	get_cp15()->read_register(CP15::CONTROL, value);
	return ( value & CP15::CONTROL_ALIGN_FAULT ) ? true : false;
}

inline bool MMU::cache_on()
{
	u32 value;
	get_cp15()->read_register(CP15::CONTROL, value);
	return ( value & CP15::CONTROL_CACHE ) ? true : false;
}