coprocessor.cpp

浙江大学的悟空嵌入式系统模拟器

/*
 *  Copyright (c) 2005 Zhejiang University, P.R.China
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */ 

//=============================================================================
/**
 *  \file    ARM/MMU.h
 *
 *  $Id: Coprocessor.cpp,v 1.4 2005/06/08 07:40:44 qilj Exp $
 *
 *  \author  Juncheng Jia <[e-mail]>
 */
//=============================================================================
#include "StdAfx.h"
#include "Coprocessor.h"

namespace ARM {

const std::string CP15::reg_name_[17] = {
	"id code", "cache type",
	"control", 
	"translation table base",
	"domain",
	"reserve",
	"fault status",
	"fault address",
	"cache funcions",
	"tlb functions",
	"cache lockdown",
	"tlb lockdown",
	"reserve",
	"reserve",
	"process id",
	"reserve",
	"reserve"
};

CP15::CP15(Core::u32 id ) : id_code_( id )
{

}

CP15::~CP15(void)
{
}

bool CP15::is_high_vectors()
{
	Core::u32 value;
	read_register(CONTROL, value);
	return (value & CONTROL_VECTOR) ? true : false;

}

void CP14::LDC(Core::Instruction_Unit binary)
{

}

void CP14::STC(Core::Instruction_Unit binary)
{

}

void CP14::MRC(Core::Instruction_Unit binary)
{
	Core::Binary_32Bit bits(binary);
	Core::u32 CRn = bits.convert_to_int(16,19);
	Core::u32 Rd = bits.convert_to_int(12, 15);
	Core::u32 value;

	switch( CRn )
	{
	case 6: // CCLKCFG
		value = cclkcfg_;
		break;
	case 7: // PWRMODE
		value = pwrmode_;
		break;
	default:
		assert(0);
	}

	((Core::CPU_32Bit *)Core::Wukong_Get_System().get_cpu())->write_register(Rd, value);

}

void CP14::MCR(Core::Instruction_Unit binary)
{
	Core::Binary_32Bit bits(binary);
	Core::u32 CRn = bits.convert_to_int(16,19);
	Core::u32 Rd = bits.convert_to_int(12, 15);
	Core::u32 value;

	((Core::CPU_32Bit *)Core::Wukong_Get_System().get_cpu())->read_register(Rd, value);
	switch( CRn )
	{
	case 6: // CCLKCFG
		cclkcfg_ = value & 0xf;
		break;
	case 7: // PWRMODE
		pwrmode_ = value & 0x3;
		break;
	default:
		assert(0);
	}

}

void CP0::MAR(Core::Instruction_Unit binary)
{
	Core::Binary_32Bit bits(binary);
	Core::u32 RdHi = bits.convert_to_int(16,19);	
	Core::u32 RdLo = bits.convert_to_int(12,15);
	Core::u32 value;
	Core::CPU_32Bit * cpu = (Core::CPU_32Bit *)Core::Wukong_Get_System().get_cpu();

	cpu->read_register(RdHi, value);
	hi_ = value % 0x100;
	cpu->read_register(RdLo, value);
	lo_ = value;
}

void CP0::MRA(Core::Instruction_Unit binary)
{
	Core::Binary_32Bit bits(binary);
	Core::u32 RdHi = bits.convert_to_int(16,19);	
	Core::u32 RdLo = bits.convert_to_int(12,15);
	Core::u32 value;
	Core::CPU_32Bit * cpu = (Core::CPU_32Bit *)Core::Wukong_Get_System().get_cpu();

	// sign extend
	if(hi_ & 0x80)
		value = 0xffffff00 | hi_;
	else
		value = hi_;
	cpu->write_register(RdHi, value);
	cpu->write_register(RdLo, RdLo);

}

}// namespace