arm_processor_i.h

浙江大学的悟空嵌入式系统模拟器

/*
*  Copyright (c) 2005 Zhejiang University, P.R.China
*
*  This program is free software; you can redistribute it and/or modify
*  it under the terms of the GNU General Public License as published by
*  the Free Software Foundation; either version 2 of the License, or
*  (at your option) any later version.
*
*  This program is distributed in the hope that it will be useful,
*  but WITHOUT ANY WARRANTY; without even the implied warranty of
*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*  GNU General Public License for more details.
*
*  You should have received a copy of the GNU General Public License
*  along with this program; if not, write to the Free Software
*  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ 

//=============================================================================
/**
*  @file    ARM/ARM_Processor_i.h
*
*  $Id: ARM_Processor_i.h,v 1.1 2005/06/08 07:40:48 qilj Exp $
*
*  @author Lingjie Qi <[e-mail]> 
*/
//=============================================================================

inline ARM_CPU::CPU_Mode ARM_CPU::get_cpu_mode()
{
	return current_mode_;
}

inline void ARM_CPU::set_cpu_mode()
{
	Core::u32 val = get_cpsr().convert_to_int(0, 7);
	ARM_CPU::CPU_Mode   cpu_mode;
	switch( val & 0xF )
	{
	case BINARY4(0000):
		cpu_mode = ARM_CPU::User;
		break;
	case  BINARY4(0001):
		cpu_mode = ARM_CPU::FIQ;
		break;
	case  BINARY4(0010):
		cpu_mode =ARM_CPU::IRQ;
		break;
	case  BINARY4(0011):
		cpu_mode = ARM_CPU::Svc;
		break;
	case  BINARY4(0111):  
		cpu_mode = ARM_CPU::Abt;
		break;
	case BINARY4(1011):
		cpu_mode = ARM_CPU::Und;
		break;
	case  BINARY4(1111):
		cpu_mode = ARM_CPU::Sys;
		break;
	}
	current_mode_ = cpu_mode;
}

inline void ARM_CPU::push_expception(ARM_CPU::CPU_Interrupt exp)
{
	exp_priority_.push(exp);
}

inline ARM_CPU::CPU_Interrupt ARM_CPU::pop_exception()
{
	//WUKONG_ASSERT(exp_priority_.empty() == false);
	if(exp_priority_.empty() == false)
	{
	CPU_Interrupt val = exp_priority_.top();
	exp_priority_.pop();
	return val;
	}
  return NO_exp;
}

inline void ARM_CPU::set_exp_priority(ARM_CPU::CPU_Interrupt pri)
{
	current_exp_priority_ = pri;
}

inline ARM_CPU::CPU_Interrupt ARM_CPU::get_exp_priority()
{
	return current_exp_priority_;
}

inline void ARM_CPU::set_cpsr(Core::u32 val)
{
	Core::Register & reg = reg_file_->get_register(ARM_CPU::CPSR);
	reg.convert_from_int(val);
}

inline void ARM_CPU::set_shifter_carry_out(Core::u8 val)
{
	shifter_carry_out_ = val;
}

inline Core::u8 ARM_CPU::get_shifter_carry_out()
{
	return shifter_carry_out_;
}

inline bool ARM_CPU::set_pc(Core::Register_Int val)
{
	Core::Register & reg = reg_file_->get_register(R15);
	reg.convert_from_int(val);
	return true;
}

inline Core::Register_Int ARM_CPU::get_pc()
{
	//Core::u32 val = 0;
	Core::Register & reg = reg_file_->get_register(R15);
	return reg.convert_to_int();
}

inline Core::Register & ARM_CPU::get_spsr()
{
	switch(current_mode_)
	{
	case Svc:
		return reg_file_->get_register(ARM_CPU::SPSR_svc);
	case IRQ:
		return reg_file_->get_register(ARM_CPU::SPSR_irq);
	case FIQ:
		return reg_file_->get_register(ARM_CPU::SPSR_fiq);
	case Abt:
		return reg_file_->get_register(ARM_CPU::SPSR_abt);
	case Und:
		return reg_file_->get_register(ARM_CPU::SPSR_und);
	default:
		break;
	}
}

inline Core::Register & ARM_CPU::get_cpsr()
{
	return reg_file_->get_register(CPSR);
}

inline Core::u32 ARM_CPU::get_factual_pc()
{
	return factual_pc_;
}

inline ARM_CPU::BreakPoint & ARM_CPU::get_current_bpt()
{
	return current_bpt_;
}

inline ARM_CPU::BreakPoint & ARM_CPU::find_bpt(Core::u32 addr)
{
	std::map<Core::u32, BreakPoint>::iterator pos;
	pos = bpt_map_.find(addr);
	assert( pos != bpt_map_.end() );
	return bpt_map_[addr];
}