📄 main.lst
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C51 COMPILER V9.01 MAIN 01/07/2011 01:47:00 PAGE 1
C51 COMPILER V9.01, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE main.c BROWSE DEBUG OBJECTEXTEND
line level source
1 /*********************************************************************
2 ** Device: A7125 **
3 ** File: main.c **
4 ** **
5 ** Description: **
6 ** This file is a sample code for your reference. **
7 ** **
8 ** Copyright (C) 2008 AMICCOM Corp. **
9 ** **
10 *********************************************************************/
11
12 #include <reg52.h>
13 #include "define.h"
14 #include "a7125reg.h"
15
16 //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
17 // I/O Declaration //
18 // TODO: USER NEED CHANGE THIS SET TO FIT SYSTEM. //
19 //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
20 sbit SCS = P1^7;
21 sbit SCK = P1^4;
22 sbit SDIO = P1^5;
23 sbit GIO1 = P1^3;
24 sbit GIO2 = P1^2;
25 #define RF_WTR GIO1
26
27
28 //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
29 // Global Variable Declaration //
30 //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
31 Uint8 idata RfBuf[64];
32 Uint8 idata TmpUint8;
33
34 //-----------------------------------------------------------------------------
35 // 64 bytes PN9 pseudo random code
36 //-----------------------------------------------------------------------------
37 const Uint8 code PN9_Tab[]=
38 { 0xFF,0x83,0xDF,0x17,0x32,0x09,0x4E,0xD1,
39 0xE7,0xCD,0x8A,0x91,0xC6,0xD5,0xC4,0xC4,
40 0x40,0x21,0x18,0x4E,0x55,0x86,0xF4,0xDC,
41 0x8A,0x15,0xA7,0xEC,0x92,0xDF,0x93,0x53,
42 0x30,0x18,0xCA,0x34,0xBF,0xA2,0xC7,0x59,
43 0x67,0x8F,0xBA,0x0D,0x6D,0xD8,0x2D,0x7D,
44 0x54,0x0A,0x57,0x97,0x70,0x39,0xD2,0x7A,
45 0xEA,0x24,0x33,0x85,0xED,0x9A,0x1D,0xE0
46 };
47
48 //-----------------------------------------------------------------------------
49 // RF ID code
50 //-----------------------------------------------------------------------------
51 const Uint8 code ID_Tab[4] =
52 {
53 0x54, 0x75, 0xC5, 0x2A
54 };
55
C51 COMPILER V9.01 MAIN 01/07/2011 01:47:00 PAGE 2
56 // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
57 // NOTE !!
58 // !! THIS CONFIG TABLE ONLY USE ON RF CRYSTAL = 16MHz !!
59 // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
60 const Uint16 code A7125Config[] =
61 {
62 // address name Descript
63 // ------- ---- ---------
64 0x00, //0x00 MODE register, only reset, not use on config
65 0x62, //0x01 MODE CTRL register, FIFO mode, Enable ARSSI, Enable AIF
66 0x00, //0x02 CALIBRATION register,
67 0x3F, //0x03 FIFO1 register,
68 0x00, //0x04 FIFO2 register,
69 0x00, //0x05 FIFO register, for fifo read/write
70 0x00, //0x06 IDDATA register, for idcode
71 0x00, //0x07 RCOSC1 register,
72 0x00, //0x08 RCOSC2 register,
73 0x00, //0x09 RCOSC3 register,
74 0x00, //0x0A CKO register,
75 0x01, //0x0B GIO1 register, WTR
76 0x01, //0x0C GIO2 register, WTR
77 0x1F, //0x0D DATARATE register,
78 0x50, //0x0E PLL1 register,
79 0x0E, //0x0F PLL2 register, RFbase 2400.001MHz
80 0x96, //0x10 PLL3 register,
81 0x00, //0x11 PLL4 register,
82 0x04, //0x12 PLL5 register,
83 0x3C, //0x13 chanel group I,
84 0x78, //0x14 chanel group II,
85 0xD7, //0x15 TX1 register,
86 0x40, //0x16 TX2 register,
87 0x10, //0x17 DELAY1 register,
88 0x61, //0x18 DELAY2 register,
89 0x62, //0x19 RX register,
90 0xA0, //0x1A RXGAIN1 register,
91 0x00, //0x1B RXGAIN2 register,
92 0x00, //0x1C RXGAIN3 register,
93 0xD2, //0x1D RXGAIN4 register,
94 0x00, //0x1E RSSI register,
95 0xE2, //0x1F ADC register,
96 0x07, //0x20 CODE1 register,
97 0x56, //0x21 CODE2 register,
98 0x2A, //0x22 CODE3 register,
99 0x06, //0x23 IFCAL1 register,
100 0x00, //0x24 IFCAL2 register, only read
101 0x05, //0x25 VCOCCAL register,
102 0x44, //0x26 VCOCAL1 register,
103 0x80, //0x27 VCOCAL2 register,
104 0x30, //0x28 VCO DEV Cal. I register,
105 0x20, //0x29 VCO DEV Cal. II register,
106 0x80, //0x2A VCO DEV Cal. III register,
107 0x00, //0x2B VCO Mod. delay register
108 0x7A, //0x2C BATTERY register,
109 0x2F, //0x2D TXTEST register,
110 0x47, //0x2E RXDEM1 register,
111 0x80, //0x2F RXDEM2 register,
112 0xF1, //0x30 CPC1 register,
113 0x11, //0x31 CPC2 register,
114 0x04, //0x32 CRYSTAL register,
115 0x45, //0x33 PLLTEST register,
116 0x18, //0x34 VCOTEST register,
117 0x10, //0x35 RF Analog Test
C51 COMPILER V9.01 MAIN 01/07/2011 01:47:00 PAGE 3
118 0xFF, //0x36 IFAT register,
119 0x37, //0x37 Channel select register,
120 0xFF //0x38 VRB register
121 };
122
123
124 /*********************************************************************
125 ** function Declaration
126 *********************************************************************/
127 void A7125_WriteReg(Uint8, Uint8);
128 Uint8 A7125_ReadReg(Uint8);
129 void StrobeCmd(Uint8 src);
130 void ByteSend(Uint8 src);
131 void A7125_Reset(void);
132 void A7125_WriteID(void);
133 void initRF(void);
134 void A7125_Config(void);
135 void A7125_Cal(void);
136 Uint8 ByteRead(void);
137 void ReadFIFO(Uint8 length);
138 void Delay1ms(Uint8 n);
139
140
141
142 /*********************************************************************
143 * main loop
144 *********************************************************************/
145 void main(void)
146 {
147 1 //initHW
148 1 P0 = 0xFF;
149 1 P1 = 0xFF;
150 1 P2 = 0xFF;
151 1 P3 = 0xFF;
152 1
153 1 initRF();
154 1 StrobeCmd(CMD_STBY);
155 1
156 1 A7125_WriteReg( TXTEST_REG, 0x17 ); // TX power = 0dBm
157 1 A7125_WriteReg( DATARATE_REG, 0x1F ); // Data rate = 2M
158 1 A7125_WriteReg( MODECTRL_REG, 0x62 ); // FIFO mode
159 1 A7125_WriteReg( PLL1_REG, 10 ); // set radio channel
160 1 A7125_WriteReg( CODE1_REG, 0x0F); // enable CRC check function
161 1
162 1 A7125_WriteReg( FIFO1_REG, 8-1 ); // set FIFO length
163 1
164 1 while(1)
165 1 {
166 2 StrobeCmd( CMD_SLEEP ); // let RF to sleep mode
167 2 Delay1ms( 8 );
168 2
169 2 StrobeCmd( CMD_STBY ); // wakeup RFIC
170 2 Delay1ms( 1 ); // wait RFIC's crystal ready
171 2
172 2 StrobeCmd( CMD_RX );
173 2 while( RF_WTR ); // wait RFIC receive data
174 2
175 2 TmpUint8 = A7125_ReadReg(MODE_REG);
176 2 if ( (TmpUint8 & 0x20) == 0 )
177 2 {
178 3 // CRC pass, read RX FIFO
179 3 ReadFIFO( 8 );
C51 COMPILER V9.01 MAIN 01/07/2011 01:47:00 PAGE 4
180 3 }
181 2 else
182 2 {
183 3 // CRC failed
184 3 }
185 2
186 2 }
187 1 }
188
189 /*********************************************************************
190 ** Err_State
191 *********************************************************************/
192 void Err_State(void)
193 {
194 1 //ERR display
195 1 //Error Proc...
196 1 while(1)
197 1 {
198 2 ;
199 2 }
200 1 }
201
202 /************************************************************************
203 ** A7125_WriteReg
204 ************************************************************************/
205 void A7125_WriteReg(Uint8 addr, Uint8 dataByte)
206 {
207 1 Uint8 i;
208 1
209 1 SCS = 0;
210 1 addr |= 0x00; //bit cmd=0,r/w=0
211 1 for(i = 0; i < 8; i++)
212 1 {
213 2 if(addr & 0x80)
214 2 SDIO = 1;
215 2 else
216 2 SDIO = 0;
217 2
218 2 SCK = 1;
219 2 _nop_();
220 2 SCK = 0;
221 2 addr = addr << 1;
222 2 }
223 1 _nop_();
224 1
225 1 //send data byte
226 1 for(i = 0; i < 8; i++)
227 1 {
228 2 if(dataByte & 0x80)
229 2 SDIO = 1;
230 2 else
231 2 SDIO = 0;
232 2
233 2 SCK = 1;
234 2 _nop_();
235 2 SCK = 0;
236 2 dataByte = dataByte << 1;
237 2 }
238 1 SCS = 1;
239 1 }
240
241 /************************************************************************
C51 COMPILER V9.01 MAIN 01/07/2011 01:47:00 PAGE 5
242 ** A7125_ReadReg
243 ************************************************************************/
244 Uint8 A7125_ReadReg(Uint8 addr)
245 {
246 1 Uint8 i;
247 1 Uint8 tmp;
248 1
249 1 SCS = 0;
250 1 addr |= 0x40; //bit cmd=0,r/w=1
251 1 for(i = 0; i < 8; i++)
252 1 {
253 2
254 2 if(addr & 0x80)
255 2 SDIO = 1;
256 2 else
257 2 SDIO = 0;
258 2
259 2 _nop_();
260 2 SCK = 1;
261 2 _nop_();
262 2 SCK = 0;
263 2
264 2 addr = addr << 1;
265 2 }
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