ieee_example.vhd

来自「The GRLIB IP Library is an integrated se」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;

entity ieee_example is
    port (
      rst       : in  std_ulogic;
      clk       : in  std_ulogic;
      hsel      : in  std_ulogic;                        -- slave select
      haddr     : in  std_logic_vector(31 downto 0);     -- address bus (byte)
      hwrite    : in  std_ulogic;                        -- read/write
      htrans    : in  std_logic_vector(1 downto 0);      -- transfer type
      hsize     : in  std_logic_vector(2 downto 0);      -- transfer size
      hburst    : in  std_logic_vector(2 downto 0);      -- burst type
      hwdata    : in  std_logic_vector(31 downto 0);     -- write data bus
      hprot     : in  std_logic_vector(3 downto 0);      -- protection control
      hreadyi   : in  std_ulogic;                        -- transfer done
      hmaster   : in  std_logic_vector(3 downto 0);      -- current master
      hmastlock : in  std_ulogic;                        -- locked access

      hreadyo   : out std_ulogic;                        -- transfer done
      hresp     : out std_logic_vector(1 downto 0);      -- response type
      hrdata    : out std_logic_vector(31 downto 0);     -- read data bus
      hsplit    : out std_logic_vector(15 downto 0));    -- split completion
end;

architecture rtl of ieee_example is
begin
end;