ahb_example.vhd

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

library ieee;
use ieee.std_logic_1164.all;

library amba;
use amba.types.all;
use amba.devices.all;

entity ahb_example is
  generic (
    ahbndx  :     integer := 0;
    memaddr :     integer := 0;
    memmask :     integer := 16#fff#);
  port (
    rst     : in  std_ulogic;
    clk     : in  std_ulogic;
    ahbsi   : in  ahb_slv_in_type;
    ahbso   : out ahb_slv_out_type);
end;

--The entity declaration above is used for interfacing the IEEE_EXAMPLE core in the GRLIB environment. It follows the layout used in some of the previous examples, facilitating generics for controlling the core.

architecture rtl of ahb_example is
  -- component declaration of IEEE-1164 based IP core
  component ieee_example
    port (
      rst       : in  std_ulogic;
      clk       : in  std_ulogic;
      hsel      : in  std_ulogic;                        -- slave select
      haddr     : in  std_logic_vector(31 downto 0);     -- address bus (byte)
      hwrite    : in  std_ulogic;                        -- read/write
      htrans    : in  std_logic_vector(1 downto 0);      -- transfer type
      hsize     : in  std_logic_vector(2 downto 0);      -- transfer size
      hburst    : in  std_logic_vector(2 downto 0);      -- burst type
      hwdata    : in  std_logic_vector(31 downto 0);     -- write data bus
      hprot     : in  std_logic_vector(3 downto 0);      -- protection control
      hreadyi   : in  std_ulogic;                        -- transfer done
      hmaster   : in  std_logic_vector(3 downto 0);      -- current master
      hmastlock : in  std_ulogic;                        -- locked access

      hreadyo   : out std_ulogic;                        -- transfer done
      hresp     : out std_logic_vector(1 downto 0);      -- response type
      hrdata    : out std_logic_vector(31 downto 0);     -- read data bus
      hsplit    : out std_logic_vector(15 downto 0));    -- split completion
  end component;

--The component declaration for the IEEE_EXAMPLE core is done locally in the architecture, but can also be done in a package. Note that the IEEE_EXAMPLE entity or component need not be visible outside the library. Only the AHB_EXAMPLE entity/component is to be made visible outside the library.

-- local signals, IEEE-1164
  signal hsel      : std_ulogic;                         -- slave select
  signal haddr     : std_logic_vector(31 downto 0);      -- address bus (byte)
  signal hwrite    : std_ulogic;                         -- read/write
  signal htrans    : std_logic_vector(1 downto 0);       -- transfer type
  signal hsize     : std_logic_vector(2 downto 0);       -- transfer size
  signal hburst    : std_logic_vector(2 downto 0);       -- burst type
  signal hwdata    : std_logic_vector(31 downto 0);      -- write data bus
  signal hprot     : std_logic_vector(3 downto 0);       -- protection control
  signal hreadyi   : std_ulogic;                         -- transfer done
  signal hmaster   : std_logic_vector(3 downto 0);       -- current master
  signal hmastlock : std_ulogic;                         -- locked access
  signal hreadyo   : std_ulogic;                         -- transfer done
  signal hresp     : std_logic_vector(1 downto 0);       -- response type
  signal hrdata    : std_logic_vector(31 downto 0);      -- read data bus
  signal hsplit    : std_logic_vector(15 downto 0);      -- split completion

--Local signal declarations are made for the interfacing of the IEEE_EXAMPLE. In this example, the names and types happen to be the same as used for the type records defined in GRLIB AMBA library. When this is not the case, conversion between Std_ULogic_Vector and Std_Logic_Vector might be required.

-- configuration
  constant hconfig : ahb_config_type := (
    0      => ahb_device_reg (VENDOR_EXAMPLE, EXAMPLE_AHB, 0, 0, 0),
    4      => ahb_membar(memaddr, '0', '0', memmask),
    others => X"00000000");

--The plug&play configuration utilizes the constants declared in the GRLIB AMBA 憈ypes