apbuart.c

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

      /*status bits error*/
      return 14;
    }
    if( (*status >> 20) & 0x3F != FIFOSIZE ) {
      /*tcnt error*/
      return 15;
    }
    
   *control = ENABLE_TX | ENABLE_RX | LOOP_BACK;
    
    i = 0;

#if SHORT_TEST == 0    
#if FIFOSIZE == 1
    while( (*status & 7) != 7) {
      if( i > (int)( FIFOSIZE * ( (FREQUENCY * 1E6) / BAUDRATE) ) ) {
	/*transmission not finished on time.status bits not set correctly*/
	return 16;
      }
      i++;
    }
#else
    while( (*status & 0x403) != 0x403 ) {
      if( i > (int)( FIFOSIZE * ( (FREQUENCY * 1E6) / BAUDRATE) ) ) {
	/*transmission not finished on time.status bits not set correctly*/
	return 16;
      }
      i++;
    }
#endif
#else
#if FIFOSIZE == 1
    while( (*status & 7) != 7)
      ; 
#else
    while( (*status & 0x403) != 0x403)
      ; 
#endif
#endif
    
    for(i = 0; i < FIFOSIZE; i++) {
      temp = *data;
      if(i == 0 && temp != (int) test[ (FIFOSIZE * 2 - 1) % testsize ] ) {
	/*incorrect data received*/
	return 18;
      }
      if( i != 0 && temp != (int) test[ i % testsize ] ) {
	/*incorrect data received*/
	return 19;
      }
    }

    *control = DISABLE;

    /*******************************
     *RECEIVER OVERFLOW TEST
     *******************************/
    
    *control = ENABLE_RX | ENABLE_TX | LOOP_BACK;
    
    for(i = 0; i < FIFOSIZE; i++ ) {
      *data = test[i % testsize];
    }  
    
    while( (*status & 4) == 0)
      ;

    *data = test[0];
    
    i = 0;

#if SHORT_TEST == 0
#if FIFOSIZE == 1
    while( (*status & 7) != 7) {
      if( i > (int)( FIFOSIZE * ( (FREQUENCY * 1E6) / BAUDRATE) ) ) {
	/*transmission not finished on time.status bits not set correctly*/
	return 20;
	i++;
      }
    }
#else
    while( (*status & 0x407) != 0x407 ) {
      if( i > (int)( FIFOSIZE * ( (FREQUENCY * 1E6) / BAUDRATE) ) ) {
	/*transmission not finished on time.status bits not set correctly*/
	return 20;
	i++;
      }
    }
    if( ((*status >> 26) & 0x3F ) != FIFOSIZE ) {
      /*rcnt error*/
      return 21;
    }
#endif
#else
#if FIFOSIZE == 1
    while( (*status & 7) != 7 ) 
      ;
#else
    while( (*status & 0x407) != 0x407 ) 
      ;
#endif
#endif

    if( (*status & 0x10) != 0 ) {
      /*ovf bit error*/
      return 22;
    }

    for(i = 0; i < FIFOSIZE + 1; i++ ) {
      temp = *data;
      if( (i == FIFOSIZE) && (temp != test[0]) ) {
	/*receive data error*/
	return 23;
      } 
      
      if((i < FIFOSIZE) && temp != test[i % testsize] ) {
	/*receive data error*/
	return 24;
      }
    }	
#if FIFOSIZE == 1 
    if( *status != 0x6 ) {
      /*status bit error*/
      return 25;
    }
#else
    if( *status != 0x86 ) {
      /*status bit error*/
      return 25;
    }
#endif    
    
    for(i = 0; i < FIFOSIZE; i++) {
      *data = test[i % testsize];
    }
    
    while( !(*status & 4) ) 
      ;
    
    *data = test[12];
    
    while( !(*status & 4) ) 
      ;
    
    *data = test[21];
    
    while( !(*status & 2) && !(*status & 4) )
      ;

    if( (*status & 0x10) == 0 ) {
      /*ovf error*/
      return 26;
    }

    for(i = 0; i < FIFOSIZE + 1; i++ ) {
      while( !(*status & 1))
	;
      temp = *data;
      if(i == FIFOSIZE) {
	if( temp != test[21]) {
	  /*receive data error*/
	  return 27;
	} 
      } else {
	if( temp != test[i % testsize] ) {
	  /*receive data error*/
	  return 28;
	}
      }
    }
    
    *data = test[0];
   
    while( !(*status & 4) || !(*status & 2))
      ;
    while( !(*status & 1))
      ;
    temp = *data;
    
    while( (*status & 1)) 
      ;

#if FIFOSIZE == 1
    if( *status != 0x16 ) {
      /*status bit error*/
      return 29;
    }
    *status = 0;
    if( *status != 0x6 ) {
      /*status bit error*/
      return 30;
    }
#else
    if( *status != 0x96 ) {
      /*status bit error*/
      return 29;
    }
    *status = 0;
    if( *status != 0x86 ) {
      /*status bit error*/
      return 30;
    }
#endif

    *control = DISABLE;

#if SHORT_TEST == 0
    /*************************
     *INTERRUPT TESTS
     *************************/
    
    catch_interrupt(irqhandler1, 2);

    *control = ENABLE_RX | ENABLE_TX | RX_INT | TX_INT | 
               LOOP_BACK | FLOW_CONTROL;

    enable_irq(2);
    
    *data = test[irqtx];
    irqtx++;
    
    while(1) {
      if(irqrx > 100000) {
	break;
      }
    }
    
#if FIFOSIZE != 1 
    
    while((*status & 1) || !(*status & 4) || !(*status & 2) ) {
      temp = *data;
    }
    
    irqrx = 0;
    irqtx = 0;
    
    
    *control = ENABLE_RX | ENABLE_TX | LOOP_BACK | FLOW_CONTROL | 
               FIFO_RX_INT | FIFO_TX_INT; 
        
    catch_interrupt(irqhandler2, 2);
    enable_irq(2);
    
    while(1) {
      if(irqrx > 100000) {
	break;
      }
    }
#endif
#endif
        
#if SHORT_TEST == 0
    /**************************************
     *FLOW-CONTROL TEST IN LOOPBACK MODE
     **************************************/
    
    while((*status & 1) || !(*status & 4) || !(*status & 2) ) {
      temp = *data;
    }
    
    *control = ENABLE_RX | ENABLE_TX | LOOP_BACK | FLOW_CONTROL;

    for(i = 0; i < FIFOSIZE; i++) {
      *data = test[i % testsize];
    }
    
    while( !(*status & 4) ) 
      ;
    
    *data = test[0];
    
    while( !(*status & 4 ) )
      ;
    
    *data = test[1];

    i = 0;
    while(i < (int)(FREQUENCY / BAUDRATE) ) {
      i++;
    }
    
    if( (*status & 4) ) {
      /*flow control error*/
      return 36;
    }
    
    for(i = 0; i < FIFOSIZE; i++) {
      temp = *data;
      if(temp != (int) test[i % testsize] ) {
	/*flow control error*/
	return 37;
      }
    }
    
    while(!(*status & 1)) 
      ;

    temp = *data;

    while( !(*status & 4) || !(*status & 2) )
      ; 
    
    temp = *data;

    if(temp != (int) test[1] ) {
      /*flow control error*/
      return 38;
    }

#endif

#endif
    
    /*******************************************************************
     *  Test of parity and break in an interactive mode where
     *  an external terminal is used.Framing errors are not yet tested
     *******************************************************************/ 

#if INTERACTIVE == 1
    /*parity*/
    *control = ENABLE_TX | ODD_PARITY;
    
    sendstring(oddpartest, ODD_PARITY, sizeof oddpartest / sizeof oddpartest[0]);
 
    *control = ENABLE_TX | ENABLE_RX | ODD_PARITY | RX_INT;
    
    catch_interrupt(irqhandler3, 2);
    enable_irq(2);
    
    interactive = 0;
    
    while(interactive < 5)
      ;
    
    *control = ENABLE_TX | ODD_PARITY;

    sendstring(oddpartest2, ODD_PARITY, sizeof oddpartest2 / sizeof oddpartest2[0]); 
    
    interactive = 0;

    catch_interrupt(irqhandler4, 2);
    enable_irq(2);
    
    *control = ENABLE_TX | ENABLE_RX | ODD_PARITY | RX_INT;
      
    while(interactive < 5)
      ;
     
    *control = ENABLE_RX | ENABLE_TX | EVEN_PARITY;
   
    sendstring(evenpartest, EVEN_PARITY, sizeof evenpartest / sizeof evenpartest[0]); 
    
    *control = ENABLE_TX | ENABLE_RX | EVEN_PARITY | RX_INT;
    
    catch_interrupt(irqhandler3, 2);
    enable_irq(2);

    interactive = 0;
    while(interactive < 5) 
      ;

    /*break*/

    *control = ENABLE_RX | ENABLE_TX | EVEN_PARITY;

    sendstring(breaktest, EVEN_PARITY, sizeof breaktest / sizeof breaktest[0]);
 
    catch_interrupt(irqhandler5, 2);
    enable_irq(2);
    
    *control = ENABLE_RX | ENABLE_TX | EVEN_PARITY | RX_INT;
   
    interactive = 0;
    while(!interactive)
      ;

    *control = ENABLE_RX | ENABLE_TX | EVEN_PARITY;
    
    sendstring(testok, EVEN_PARITY, sizeof testok / sizeof testok[0]);

#endif
    *control = DISABLE;

   return 0;
      
}