apbuart_test.c

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

#include <stdio.h>

#define APBUART_ADDRESS 0x80000100

#define DISABLE 0x0
#define ENABLE_RX 0x1
#define ENABLE_TX 0x2
#define RX_INT 0x4
#define TX_INT 0x8
#define EVEN_PARITY 0x20
#define ODD_PARITY 0x30
#define LOOP_BACK 0x80
#define FLOW_CONTROL 0x40
#define FIFO_TX_INT 0x200
#define FIFO_RX_INT 0x400

/* 
 * uart[0] = data
 * uart[1] = status
 * uart[2] = control
 * uart[3] = scaler
 */

static volatile int *uart = (int *) APBUART_ADDRESS;
static char test[] = "40ti94a+0ygiyu05yhap5yi4h+a+iiyxhi4k59j0q905jkoyphoptjrhia4iy0+4";
static int testsize = sizeof test / sizeof test[0];

int apbuart_test(void) 
{
        int temp;
        int i;  
        int fifosize;

        /* set scaler to low value to speed up simulations */
        uart[3] = 1;
        
        /* determine fifosize */
        uart[2] = ENABLE_TX;
        while( ((uart[1] >> 2) & 0x1) != 1 ) {}
        uart[2] = DISABLE;
        
        fifosize = 0;
        do {
                fifosize++;
                uart[0] = 0;
        } while ( ((uart[1] >> 20) & 0x3F) == fifosize );
        fifosize--;
     
        uart[2] = ENABLE_RX | ENABLE_TX;
  
        /*set counters to 0, and status bits to reset values*/
  
        while( (uart[1] & 1) || !(uart[1] & 4) || !(uart[1] & 2) ) {
                temp = uart[0];
        }
 
        temp = 0;
        uart[2] = DISABLE;
        uart[1] = 0;
        

        /*
         *  TRANSMITTER TEST
         */

        if(fifosize > 1) {
                if(((uart[1] & 0x80) == 0) ) {
                        /*th bit incorrect*/
                        return 4;
                }
        }
        

        uart[0] = (int) test[0];
        
        if( (uart[1] & 4) == 1) {
                /*te bit incorrect*/
                return 1;
        }

        if(uart[1] & 2 == 0) {
                /*ts bit incorrect*/
                return 2;
        }
        
        if (fifosize > 1) {
                for(i = 1; i < fifosize; i++) {
                        uart[0] = (int) test[i % testsize];
                }
        
                if(((uart[1] & 0x80) == 1) ) {
                        /*th bit incorrect*/
                        return 5;
                }
                
                if( ((uart[1] >> 20) & 0x3F) != fifosize ) {
                        /*tcnt error*/
                        return 6;
                }

                if ( uart[1] & 0x200 == 0) {
                        /*tf bit incorrect*/
                        return 7;
                }

                
        }
        
        /*
         *  RECEIVER TEST (WITH LOOPBACK)
         */

        if(uart[1] & 1 != 0) {
                /*dr bit incorrect*/
                return 7;
        }

        uart[2] = ENABLE_TX | ENABLE_RX | LOOP_BACK;
    
        i = 0;

        if (fifosize == 1) {
                while((uart[1] & 1) == 0) {}
        } else {
                while((uart[1] & 0x400) == 0) {}
        }
        
                        
        if( (uart[1] & 1) == 0 ) {
                /*dr bit incorrect*/
                return 8;
        }
        
        if( fifosize > 1 ) {
                if( ((uart[1] >> 26) & 0x3F) != fifosize) {
                        /*rcnt error*/
                        return 9;
                }
                
                if( (uart[1] & 0x100) == 0) {
                        /*rhalffull error */
                        return 10;
                }
                
                if( (uart[1] & 0x400) == 0) {
                        /*rfull error */
                        return 11;
                }
        }
        
        for(i = 0; i < fifosize; i++) {
                temp = uart[0];
                if(temp != test[i % testsize] ) {
                        /*data error*/
                        return 12;
                }
        }
        
        if(fifosize > 1) {
                if( (uart[1] & 0x100) != 0 ) {
                        /*rhalffull error*/
                        return 13;
                }
                
                if( ((uart[1] >> 26) & 0x3F) != 0) {
                        /*rcnt error*/
                        return 14;
                }
                
                
                if( (uart[1] & 0x400) != 0) {
                        /*rfull error */
                        return 11;
                }
        }


        if( uart[1] & 1 != 0 ) {
                /*dr bit error*/
                return 12;
        }
        
        uart[2] = DISABLE;
        return 0;
      
}