ramtest.c

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

#include "testmod.h"
#define CCTRL_IFP (1<<15)
#define CCTRL_DFP (1<<14)

extern rsysreg(int addr);
extern wsysreg(int *addr, int data);
extern cache_disable();
extern cache_enable();

cramtest()
{
	volatile double mrl[1024 + 8];
	int i; 
	int ilinesz, dlinesz, dbytes, ibytes, itmask, dtmask, isets, dsets; 
	int icconf, dcconf, cachectrl;

	flush();
	cache_enable();
	icconf = rsysreg(8);
	dcconf = rsysreg(12);

//	report(CRAM_TEST);

	isets = ((icconf >> 24) & 3) + 1;
	ilinesz = 1 << (((icconf >> 16) & 7) + 2);
	ibytes = (1 << (((icconf >> 20) & 15) + 10)) * isets;
	itmask = (ilinesz - 1) | (0x80000000 - ibytes);
	dsets = ((dcconf >> 24) & 3) + 1;
	dlinesz = 1 << (((dcconf >> 16) & 7) + 2);
	dbytes = (1 << (((dcconf >> 20) & 15) + 10)) * dsets;
	dtmask = (dlinesz - 1) | (0x80000000 - dbytes);

	do cachectrl = rsysreg(0); while(cachectrl & (CCTRL_IFP | CCTRL_DFP));


	/* dcache data ram */

	if (ddramtest1(dbytes, mrl,0x55555555)) fail(CMEM_TEST, 1);
	if (ddramtest2(dbytes, mrl,0xaaaaaaaa)) fail(CMEM_TEST, 2);

	cache_disable();

	/* dcache tag ram */

	if (dtramtest(dbytes, (0xaaaaaa00 & dtmask), dtmask, dlinesz,
	    0xaaaaaaaa)) fail(CMEM_TEST, 3);
	if (dtramtest(dbytes, (0x55555500 & dtmask), dtmask, dlinesz,
	    0x55555555)) fail(CMEM_TEST, 4);

	/* icache data ram */

	if (idramtest(ibytes, 0x55555555)) fail(CMEM_TEST, 5);
	if (idramtest(ibytes, 0xaaaaaaaa)) fail(CMEM_TEST, 6);

	/* icache tag ram */

	if (itramtest(ibytes, itmask, ilinesz, 0xaaaaaaaa)) fail(CMEM_TEST, 7);
	if (itramtest(ibytes, itmask, ilinesz, 0x55555555)) fail(CMEM_TEST, 8);
	flush();
	cache_enable();
	return(0);

}



/* test dcache data ram */
ddramtest1(int bytes, int *buf, int init)
{
	asm ("

	mov	%o0, %o4
	mov	%o2, %o3
1:
	subcc	%o4, 8, %o4
	bg 1b
	std	%o2, [%o4 + %o1]

	mov	%o0, %o4
1:
	subcc	%o4, 8, %o4
	bg 1b
	ldd	[%o4 + %o1], %g0

	mov	%o0, %o4
	subcc	%o4, 4, %o4
	ld	[%o4 + %o1], %o3
2:
	subcc	%o3, %o2, %g0
	bne 	6f
	subcc	%o4, 4, %o4
	bg,a 2b
	ld	[%o4 + %o1], %o3

	retl
	mov	0, %o0

6: 	mov	1, %o0

	");
}

/* test dcache data ram */
ddramtest2(int bytes, int *buf, int init)
{
	asm ("

	mov	%o0, %o4
	mov	%o2, %o3
1:
	subcc	%o4, 8, %o4
	bg 1b
	std	%o2, [%o4 + %o1]

	mov	%o0, %o4
	subcc	%o4, 4, %o4
	ld	[%o4 + %o1], %o3
2:
	subcc	%o3, %o2, %g0
	bne 	6f
	subcc	%o4, 4, %o4
	bg,a 2b
	ld	[%o4 + %o1], %o3


	retl
	mov	0, %o0

6: 	mov	1, %o0

	");

}

/* test icache data ram */
idramtest(int bytes, int init)
{
	asm ("

	mov	%o0, %o4	! init data ram
	subcc	%o4, 4, %o4
	sta	%o1, [%o4] 0xd
1:
	lda	[%o4] 0xd, %o5
	subcc	%o5, %o1, %g0
	bne 	6f
	subcc	%o4, 4, %o4
	bg 1b
	sta	%o1, [%o4] 0xd

	retl
	mov	0, %o0

6: 	mov	1, %o0
	");

}


itramtest(int bytes, int mask, int linesz, int init)
{
	asm ("

	mov	%o0, %o5	! init data ram
	subcc	%o5, %o2, %o5
	sta	%o3, [%o5] 0xc
1:
	lda	[%o5] 0xc, %o4
	xor  	%o4, %o3, %o4
	andcc	%o4, %o1, %o4
	bne 	6f
	subcc	%o5, %o2, %o5
	bg 1b
	sta	%o3, [%o5] 0xc

	retl
	mov	0, %o0

6: 	mov	1, %o0
	");
}

dtramtest(int bytes, int addr, int mask, int linesz, int init)
{
	asm ("

	mov	%o0, %o5	! init data ram
	subcc	%o5, %o3, %o5
	sta	%o4, [%o1 + %o5] 0xe

1:
	lda	[%o1 + %o5] 0xe, %g2
	xor  	%g2, %o4, %g2
	andcc	%g2, %o2, %g2
	bne 	6f
	subcc	%o5, %o3, %o5
	bg 1b
	sta	%o4, [%o1 + %o5] 0xe

	retl
	mov	0, %o0

6: 	mov	1, %o0
	");
}