ftsrctrl.c

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

/*******************************************************************************
 *Testsequence for the Fault tolerant version of the PROM/SRAM controller
 *******************************************************************************/
#include "ftlib.h"

#define EDACEN     1
#define AHBSTATEN  1
#define SRAM       0x40000000   
#define PROM       0x0          
#define AHBSTAT    0x80000500  
#define CONF       0x80000008   
#define LEONMST    0            

#define DISABLE    0
#define CBSE       0x21          
#define SRAMEN     0x200
#define PROMEN     0x100
#define RB         0x400
#define WB         0x800
#define CLEAR      0xFF000

static volatile int *psram = (int *) SRAM;
static volatile int *pprom = (int *) PROM;
static volatile int *pconf = (int *) CONF;
static volatile int *ahbstat = (int *) AHBSTAT;

int ftsrctrl_test(void) {
  int temp;
  int i;
  int cachectrl;
  //Disable cache
  cachectrl = cache_disable();
 
#if EDACEN == 1
  //Enable sram edac and wb
  pconf[0] = RB | WB | PROMEN | CBSE; 
  //single error on SRAM
  pprom[0] = 0x12345678;
  if( pprom[0] != 0x12345278 ) {
    //edac or write diagnostics error
    return 1;
  }
  if( (pconf[0] & 0xFF) != CBSE) return 2; 

#if AHBSTATEN == 1
  if( (ahbstat[0] & 0x3FF) != 0x302) return 3;
  if( ahbstat[1] != (int)(&pprom[0])) return 4;
  ahbstat[0] = 0;
  if (((ahbstat[0] >> 8) & 0x3) != 0) return 5;
  pprom[1] = 0x12345678;
  if( pprom[1] != 0x12345278 ) return 6; 
  if( (ahbstat[0] & 0x3FF) != 0x302) return 7;
  if( ahbstat[1] != (int)(&pprom[1])) return 8;
#endif
  
  if( (pconf[0] & 0xFF) != CBSE) return 9; 
 
  pconf[0] = DISABLE;
  if(pconf[0] != 0) return 10;
#endif
  cache_reset(cachectrl);
  return 0;
}