prom.s

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

#define MCFG1 0x233
#define MCFG2 0xe6B84e60
#define MCFG3 0x000ff000
#define L2MCTRLIO 0x80000000
#define RAMSTART  0x40000000
#define RAMSIZE   0x00100000

	.seg	"text"
	.proc	0
	.align	4
	.global start
start:

	flush
	set 0x10c0, %g1		! init IU
	mov %g1, %psr
	mov %g0, %wim
	mov %g0, %tbr
	mov %g0, %y
	nop
	set  0x1000f, %g1
	sta %g1, [%g0] 2
	
2:
	mov %asr17, %g3
	and %g3, 0x1f, %g3
	mov %g0, %g4
	mov %g0, %g5
	mov %g0, %g6
	mov %g0, %g7
1:
	mov %g0, %l0
	mov %g0, %l1
	mov %g0, %l2
	mov %g0, %l3
	mov %g0, %l4
	mov %g0, %l5
	mov %g0, %l6
	mov %g0, %l7
	mov %g0, %o0
	mov %g0, %o1
	mov %g0, %o2
	mov %g0, %o3
	mov %g0, %o4
	mov %g0, %o5
	mov %g0, %o6
	mov %g0, %o7
	subcc %g3, 1, %g3
	bge 1b
	save

	mov	2, %g1
	mov	%g1, %wim
	set 0x10e0, %g1		! enable traps
	mov %g1, %psr
	nop; nop; nop;


	set L2MCTRLIO, %g1
	set MCFG1, %g2
	st  %g2, [%g1]
	set MCFG2, %g2
	st  %g2, [%g1+4]
	set MCFG3, %g2
	st  %g2, [%g1+8]

	set RAMSTART+ RAMSIZE-32, %fp
	sub %fp, 96, %sp

	set RAMSTART, %g1
	jmp %g1
	nop

.align	32