ftlib.h

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) de

#define IRQMPADR 0x80000200  //Address to irq controller
#define IRQ 11 //Interrupt line used by the status module 

struct databits {
  unsigned d31 : 1;
  unsigned d30 : 1;
  unsigned d29 : 1;
  unsigned d28 : 1;
  unsigned d27 : 1;
  unsigned d26 : 1;
  unsigned d25 : 1;
  unsigned d24 : 1;
  unsigned d23 : 1;
  unsigned d22 : 1;
  unsigned d21 : 1;
  unsigned d20 : 1;
  unsigned d19 : 1;
  unsigned d18 : 1;
  unsigned d17 : 1;
  unsigned d16 : 1;
  unsigned d15 : 1;
  unsigned d14 : 1;
  unsigned d13 : 1;
  unsigned d12 : 1;
  unsigned d11 : 1;
  unsigned d10 : 1;
  unsigned d9 : 1;
  unsigned d8 : 1;
  unsigned d7 : 1;
  unsigned d6 : 1;
  unsigned d5 : 1;
  unsigned d4 : 1;
  unsigned d3 : 1;
  unsigned d2 : 1;
  unsigned d1 : 1;
  unsigned d0 : 1;
};

struct checkbits {
  unsigned unused : 25;
  unsigned c6 : 1;
  unsigned c5 : 1;
  unsigned c4 : 1;
  unsigned c3 : 1;
  unsigned c2 : 1;
  unsigned c1 : 1;
  unsigned c0 : 1;
};


extern int *lreg;
//integer power of 2
extern int pow2(int exp);

//returns (32,7) BCH checksum 
extern int encode(int data);

/*modifies a checksum cbits so that it will
generate a single error in bit nr "bit" if mode=0
with mode=1 different multiple errors are generated*/
extern int scramble(int cbits, int bit, int mode);

//disables the caches in the Leon3. Returns the
//previous cache controller conf register value
extern int cache_disable(void);


//Sets the cache controller conf reg to cctrl
extern void cache_reset(int cctrl);

extern void enable_irq (int irq);

extern void disable_irq (int irq); 

extern void clear_irq (int irq); 

extern void force_irq (int irq);