clkbuf_actel.vhd

来自「The GRLIB IP Library is an integrated se」· VHDL 代码 · 共 34 行

----------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2004 GAISLER RESEARCH
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: 	clkbuf_actel
-- File:	clkbuf_actel.vhd
-- Author:	Marko Isomaki - Gaisler Research
-- Description:	Clock buffer generator for Actel devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library actel;
use actel.actel_components.all;

entity clkbuf_actel is
  port(
    i    :  in  std_ulogic;
    o    :  out std_ulogic
  );
end entity;

architecture rtl of clkbuf_actel is
begin
  buf : hclkint port map(A => i, Y => o);  
end architecture;