clkmux.vhd

来自「The GRLIB IP Library is an integrated se」· VHDL 代码 · 共 85 行

----------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2004 GAISLER RESEARCH
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: 	clkmux
-- File:	clkmux.vhd
-- Author:	Marko Isomaki - Gaisler Research 
-- Description: Clock multiplexer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;

entity clkmux is
  port(
    sel    : in  std_ulogic;
    clk1   : in  std_ulogic;
    clk2   : in  std_ulogic;
    clkout : out std_ulogic
  );
end entity;

architecture rtl of clkmux is
  type reg_type is record
    sel : std_ulogic;
  end record;
 
  signal r1,  rin1   : reg_type;
  signal r2,  rin2   : reg_type;
  signal nr1, nrin1  : reg_type;
  signal nr2, nrin2  : reg_type; 
begin
  comb : process(sel, r1, r2, nr1, nr2, clk1, clk2) is
  variable v1    : reg_type;
  variable v2    : reg_type;
  variable nv1   : reg_type;
  variable nv2   : reg_type;                                                 
  variable sel1  : std_ulogic;
  variable sel2  : std_ulogic;
  variable clk1o : std_ulogic;
  variable clk2o : std_ulogic;
  begin
    v1 := r1; v2 := r2; nv1 := nr1; nv2 := nr2;
    sel1 := (not sel) and (not nr2.sel);
    sel2 := sel and (not nr1.sel); 

    v1.sel := sel1; v2.sel := sel2;
    nv1.sel := r1.sel; nv2.sel := r2.sel;

    clk1o := clk1 and nr1.sel; clk2o := clk2 and nr2.sel;

    clkout <= clk1o or clk2o;
    
    rin1 <= v1; rin2 <= v2; nrin1 <= nv1; nrin2 <= nv2; 
  end process;

  regs_clk1 : process(clk1) is
  begin
    if rising_edge(clk1) then r1 <= rin1; end if;
  end process;

  regs_clk2 : process(clk2) is
  begin
    if rising_edge(clk2) then r2 <= rin2; end if;
  end process;

  neg_regs_clk1 : process(clk1) is
  begin
    if falling_edge(clk1) then nr1 <= nrin1; end if;
  end process;

  neg_regs_clk2 : process(clk2) is
  begin
    if falling_edge(clk2) then nr2 <= nrin2; end if;
  end process;
end architecture;