genclkbuf.vhd

来自「The GRLIB IP Library is an integrated se」· VHDL 代码 · 共 48 行

----------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2004 GAISLER RESEARCH
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: 	genclkbuf
-- File:	genclkbuf.vhd
-- Author:	Marko Isomaki - Gaisler Research
-- Description:	Generic Clock buffer with tech wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.tech.all;
library gaisler;
use gaisler.libbuf.all; 

entity genclkbuf is
  generic(
    tech     :  integer range 0 to NTECH := inferred);
  port(
    i        :  in  std_ulogic;
    o        :  out std_ulogic
  );
end entity;

architecture rtl of genclkbuf is
begin
  gen : if (tech /= axcel) and (tech /= virtex) and (tech /= virtex2) and
     (tech /= spartan3)
  generate
    o <= i;
  end generate;
  axc : if (tech = axcel) generate
    axc : clkbuf_actel port map(i => i, o => o);
  end generate;
  xil : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) generate
    xil : clkbuf_xilinx port map(i => i, o => o);
  end generate;
end architecture;