clkbuf_xilinx.vhd

来自「The GRLIB IP Library is an integrated se」· VHDL 代码 · 共 36 行

----------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2004 GAISLER RESEARCH
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: 	clkbuf_xilinx
-- File:	clkbuf_xilinx.vhd
-- Author:	Marko Isomaki - Gaisler Research
-- Description:	Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity clkbuf_xilinx is
  port(
    i    :  in  std_ulogic;
    o    :  out std_ulogic
  );
end entity;

architecture rtl of clkbuf_xilinx is
  signal gnd  : std_ulogic;
begin
  gnd <= '0';
  buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);  
end architecture;