eth_sync.vhd

来自「The GRLIB IP Library is an integrated se」· VHDL 代码 · 共 183 行

-------------------------------------------------------------------------------
-- Entity:	eth_sync
-- File:        eth_sync.vhd
-- Author:      Marko Isomaki
-- Description: Synchronizers for Ethernet MAC
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- SYNCHRONIZER  --------------------------------------------------------------
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity one_way_sync is
  generic(
    nsync : integer range 1 to 2 := 2);
  port(
    rst  : in std_ulogic; 
    clk  : in std_ulogic;
    sin  : in std_ulogic;
    sout : out std_ulogic
  );
end entity;

architecture rtl of one_way_sync is
  type reg_type is record
    out_reg : std_ulogic;
    sreg    : std_logic_vector(nsync-1 downto 0); 
  end record; 
  
  signal r, rin : reg_type; 
begin
  comb : process(r, sin) is
  variable v     : reg_type;
  variable vsout : std_ulogic; 
  begin
    v := r;

    v.sreg(0) := sin;
    if nsync = 2 then 
      v.sreg(1) := r.sreg(0);
    end if; 
    v.out_reg := r.sreg(nsync-1);

    vsout := r.out_reg xor r.sreg(nsync-1);

    if rst = '0' then
      v.out_reg := '0'; v.sreg := (others => '0');
    end if; 
    
    rin <= v; sout <= vsout; 
  end process;
  
  reg : process(clk) is
  begin
    if rising_edge(clk) then r <= rin; end if; 
  end process; 
end architecture;

-------------------------------------------------------------------------------
-- SYNCHRONIZER WITH ACKNOWLEDGE ----------------------------------------------
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity two_way_sync is
  generic(
    nsync : integer range 1 to 2 := 2);
  port(
    rst  : in std_ulogic; 
    clk1 : in std_ulogic;
    clk2 : in std_ulogic;
    sin  : in std_ulogic;
    sout : out std_ulogic;
    ack  : out std_ulogic
  );
end entity;

architecture rtl of two_way_sync is
  type reg1_type is record
    sreg    : std_logic_vector(nsync-1 downto 0);
    outreg  : std_ulogic; 
  end record;

  type reg2_type is record
    sreg    : std_logic_vector(nsync-1 downto 0); 
    outreg  : std_ulogic; 
  end record;

  signal r1, rin1 : reg1_type;
  signal r2, rin2 : reg2_type; 
begin
  comb: process(r1, r2, sin) is
  variable v1    : reg1_type;
  variable v2    : reg2_type;
  variable vsout : std_ulogic;
  variable vack  : std_ulogic; 
  begin
    v1 := r1; v2 := r2;

    v2.sreg(0) := sin;
    v1.sreg(0) := r2.outreg;
    
    v2.outreg := r2.sreg(nsync-1);
    v1.outreg := r1.sreg(nsync-1);
        
    vsout := r2.outreg xor r2.sreg(nsync-1);
    vack := r1.outreg xor r1.sreg(nsync-1); 
      
    if nsync = 2 then
      v2.sreg(1) := r2.sreg(0);
      v1.sreg(1) := r1.sreg(0);
    end if; 
    
    if rst = '0' then
      v2.outreg := '0'; v2.sreg := (others => '0');
      v1.outreg := '0'; v1.sreg := (others => '0');
    end if; 

    rin1 <= v1; rin2 <= v2; sout <= vsout; ack <= vack; 
  end process;

  reg1 : process(clk1) is
  begin
    if rising_edge(clk1) then r1 <= rin1; end if;
  end process;

  reg2 : process(clk2) is
  begin
    if rising_edge(clk2) then r2 <= rin2; end if; 
  end process; 
end architecture;

-------------------------------------------------------------------------------
-- SIMPLE ONE WAY SYNCHRONIZER  -----------------------------------------------
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity one_way_simple_sync is
  generic(
    nsync : integer range 1 to 2 := 2);
  port(
    rst   : in std_ulogic; 
    clk   : in std_ulogic;
    sin   : in std_ulogic;
    sout  : out std_ulogic
  );
end entity; 

architecture rtl of one_way_simple_sync is
  type reg_type is record
    sreg : std_logic_vector(nsync-1 downto 0);
  end record;
  
  signal r, rin : reg_type; 
begin
  comb : process(sin, r) is
  variable v : reg_type; 
  begin
    v := r;
    v.sreg(0) := sin;
    if nsync = 2 then
      v.sreg(1) := r.sreg(0);
    end if;

    if rst = '0' then
      v.sreg := (others => '0');
    end if; 
    sout <= r.sreg(nsync-1);
    rin <= v;
  end process;

  regs : process(clk) is
  begin
    if rising_edge(clk) then r <= rin; end if;
  end process; 
  
end architecture;