dsu3.vhd

来自「The GRLIB IP Library is an integrated se」· VHDL 代码 · 共 526 行 · 第 1/2 页

    if (ahbsi.hready and ahbsi.hsel(hindex)) = '1' then
      if (ahbsi.htrans(1) = '1') then
        v.slv.hsel := '1';      
        v.slv.haddr := ahbsi.haddr(PROC_H downto 0);
        v.slv.hwrite := ahbsi.hwrite;
        v.cnt := "111";
      end if;
    end if;


    
    for i in 0 to NCPU-1 loop
      v.en(i) := r.dsuen(2) and dbgi(i).dsu;
    end loop;

    rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));    
    if ncpu = 1 then index := 0; else
      if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
    end if;

    hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
    hasel2 := r.slv.haddr(6 downto 2);
    if r.slv.hsel = '1' then
      case hasel1 is 
        
        when "000" =>  -- DSU registers
          v.slv.hready := '1';
          hrdata := (others => '0');          
          case hasel2 is
            when "00000" =>
              if r.slv.hwrite = '1' then
                v.te(index) := ahbsi.hwdata(0);
                v.be(index) := ahbsi.hwdata(1);
                v.bw(index) := ahbsi.hwdata(2);
                v.bs(index) := ahbsi.hwdata(3);
                v.bx(index) := ahbsi.hwdata(4);                
                v.bz(index) := ahbsi.hwdata(5);                
                v.reset(index) := ahbsi.hwdata(9);                
                v.halt(index) := ahbsi.hwdata(10);                
              else
                hrdata(0) := r.te(index);
                hrdata(1) := r.be(index);
                hrdata(2) := r.bw(index);
                hrdata(3) := r.bs(index);
                hrdata(4) := r.bx(index);
                hrdata(5) := r.bz(index);
                hrdata(6) := dbgi(index).dsumode;
                hrdata(7) := r.dsuen(2);
                hrdata(8) := r.dsubre(2);
                hrdata(9) := not dbgi(index).error;
                hrdata(10) := dbgi(index).halt;
                hrdata(11) := dbgi(index).pwd;
              end if;
            when "00010" =>  -- timer
              if r.slv.hwrite = '1' then
                v.timer := ahbsi.hwdata(tbits-1 downto 0);
              else
                hrdata(tbits-1 downto 0) := r.timer;
              end if;
            when "01000" =>
              if r.slv.hwrite = '1' then
                v.bn := ahbsi.hwdata(NCPU-1 downto 0);
                v.ss := ahbsi.hwdata(16+NCPU-1 downto 16);
              else
                hrdata(NCPU-1 downto 0) := r.bn;
                hrdata(16+NCPU-1 downto 16) := r.ss; 
              end if;
            when "01001" =>
              if r.slv.hwrite = '1' then
                v.bmsk(NCPU-1 downto 0) := ahbsi.hwdata(NCPU-1 downto 0);
                v.dmsk(NCPU-1 downto 0) := ahbsi.hwdata(NCPU-1+16 downto 16);
              else
                hrdata(NCPU-1 downto 0) := r.bmsk;
                hrdata(NCPU-1+16 downto 16) := r.dmsk;
              end if;
            when "10000" =>
	      if TRACEN then
	        hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
	        hrdata(1 downto 0) := tr.dcnten & tr.enable;
	        if r.slv.hwrite = '1' then
	          tv.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16); 
	          tv.dcnten := ahbsi.hwdata(1);
	          tv.enable := ahbsi.hwdata(0);
	        end if;
	      end if;
            when "10001" =>
	      if TRACEN then
	        hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
	        if r.slv.hwrite = '1' then
	          tv.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0); 
	        end if;
	      end if;
            when "10100" =>
	      if TRACEN then
	        hrdata(31 downto 2) := tr.tbreg1.addr; 
	        if r.slv.hwrite = '1' then
	          tv.tbreg1.addr := ahbsi.hwdata(31 downto 2); 
	        end if;
	      end if;
            when "10101" =>
	      if TRACEN then
	        hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write; 
	        if r.slv.hwrite = '1' then
	          tv.tbreg1.mask := ahbsi.hwdata(31 downto 2); 
	          tv.tbreg1.read := ahbsi.hwdata(1); 
	          tv.tbreg1.write := ahbsi.hwdata(0); 
	        end if;
	      end if;
            when "10110" =>
	      if TRACEN then
	        hrdata(31 downto 2) := tr.tbreg2.addr; 
	        if r.slv.hwrite = '1' then
	          tv.tbreg2.addr := ahbsi.hwdata(31 downto 2); 
	        end if;
	      end if;
            when "10111" =>
	      if TRACEN then
	        hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write; 
	        if r.slv.hwrite = '1' then
	          tv.tbreg2.mask := ahbsi.hwdata(31 downto 2); 
	          tv.tbreg2.read := ahbsi.hwdata(1); 
	          tv.tbreg2.write := ahbsi.hwdata(0); 
	        end if;
	      end if;
            when others =>
          end case;

        when "010"  =>  -- AHB tbuf
	  if TRACEN then
            if r.cnt(1 downto 0) = "10" then v.slv.hready := '1'; end if;
            vabufi.enable := not (tr.enable and not r.act);
            case tr.haddr(3 downto 2) is
            when "00" =>
	      hrdata := tbo.data(127 downto 96);
	      if r.slv.hwrite = '1' then 
	        vabufi.write(3) := vabufi.enable;
	      end if;
            when "01" =>
	      hrdata := tbo.data(95 downto 64);
	      if r.slv.hwrite = '1' then 
	        vabufi.write(2) := vabufi.enable;
	      end if;
            when "10" =>
	      hrdata := tbo.data(63 downto 32);
	      if r.slv.hwrite = '1' then 
	        vabufi.write(1) := vabufi.enable;
	      end if;
            when others =>
	      hrdata := tbo.data(31 downto 0);
	      if r.slv.hwrite = '1' then 
	        vabufi.write(0) := vabufi.enable;
	      end if;
	    end case;
	  end if;
        when "011" | "001"  =>  -- IU reg file, IU tbuf
          iuacc := '1';
          hrdata := dbgi(index).data;
          if r.cnt(1 downto 0) = "10" then v.slv.hready := '1'; end if;
        when "100" =>  -- IU reg access
          iuacc := '1';
          hrdata := dbgi(index).data;
          if r.cnt(1 downto 0) = "11" then v.slv.hready := '1'; end if;
        when "111" => -- DSU ASI
          if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
          if (dbgi(index).crdy = '1') or (r.cnt = "000") then v.slv.hready := '1'; end if;
          hrdata := dbgi(index).data;          
        when others =>
          v.slv.hready := '1';
      end case;
      if (r.slv.hready and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;      
    end if;

    if r.slv.hsel  = '1' then
      if r.slv.hwrite = '1' then v.slv.hdata := ahbsi.hwdata;
      else v.slv.hdata := hrdata; end if;
    end if;
    
    if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') and (ahbsi.htrans(1) = '0') then
      v.slv.hready := '1';
    end if;
    
    if rst = '0' then
      v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
      v.dmsk := (others => '0');
      v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
      for i in 0 to NCPU-1 loop
        v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2); 
        v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2); 
        v.bs(i) := '0'; v.te(i) := '0';
      end loop;
      tv.ahbactive := '0'; tv.enable := '0';
      tv.hsel := '0'; tv.dcnten := '0';
      tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
      tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
      v.slv.hready := '1'; v.halt := (others => '0'); 
    end if;

    rin <= v; trin <= tv; tbi <= vabufi;

    for i in 0 to NCPU-1 loop
      dbgo(i).tenable <= r.te(i);
      dbgo(i).dsuen <= r.en(i);  
      dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
      if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
        dbgo(i).denable <= iuacc;
      else
        dbgo(i).denable <= '0';
      end if;
      dbgo(i).step <= r.ss(i);    
      dbgo(i).berror <= r.be(i);
      dbgo(i).bsoft <= r.bs(i);
      dbgo(i).bwatch <= r.bw(i);
      dbgo(i).btrapa <= r.bx(i);
      dbgo(i).btrape <= r.bz(i);
      dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
      dbgo(i).ddata <= r.slv.hdata;    
      dbgo(i).dwrite <= r.slv.hwrite;
      dbgo(i).halt <= r.halt(i);
      dbgo(i).reset <= r.reset(i);
      dbgo(i).timer(tbits-1 downto 0) <= r.timer; 
      dbgo(i).timer(30 downto tbits) <= (others => '0');      
    end loop;
    
    ahbso.hconfig <= hconfig;
    ahbso.hresp <= HRESP_OKAY;
    ahbso.hready <= r.slv.hready;
    ahbso.hrdata <= r.slv.hdata;    
    ahbso.hsplit <= (others => '0');
    ahbso.hcache <= '0';
    ahbso.hirq   <= hirq;
    ahbso.hindex <= hindex;
    

    dsuo.active <= r.act;
    dsuo.tstop <= tstop;
    
  end process;
  
  reg : process(clk)
  begin if rising_edge(clk) then r <= rin; end if; end process;
    
  tb0 : if TRACEN generate
    treg : process(clk)
    begin if rising_edge(clk) then tr <= trin; end if; end process;
    mem0 : tbufmem
    generic map (tech => tech, tbuf => kbytes) port map (clk, tbi, tbo);
-- pragma translate_off
    bootmsg : report_version 
    generic map ("dsu3_" & tost(hindex) &
    ": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
  end generate;
    
  notb : if not TRACEN generate
-- pragma translate_off
    bootmsg : report_version 
    generic map ("dsu3_" & tost(hindex) &
    ": LEON3 Debug support unit");
-- pragma translate_on
  end generate;

end;