spartan3_ddr1.opj

fpga-sdram开发板-sch,本原理图是xilinx公司s3系列开发板的sdram

(ExpressProject ""
  (ProjectVersion "19981106")
  (ProjectType "PCB")
  (Folder "Design Resources"
    (Folder "Library")
    (File ".\spartan3_ddr1.dsn"
      (Type "Schematic Design"))
    (BuildFileAddedOrDeleted "x")
    (CompileFileAddedOrDeleted "x")
    (NoModify)
    (DRC_Scope "0")
    (DRC_Action "1")
    (DRC_Create_Warnings "FALSE")
    (DRC_Check_Ports "TRUE")
    (DRC_Check_Off-Page_Connectors "TRUE")
    (DRC_Identical_References "TRUE")
    (DRC_Type_Mismatch "TRUE")
    (DRC_Report_Ports_and_Off-page_Connectors "FALSE")
    (DRC_SDT_Compatibility "FALSE")
    (DRC_Report_Off-grid_Objects "FALSE")
    (DRC_Check_Unconnected_Nets "TRUE")
    (DRC_Report_Netnames "FALSE")
    (DRC_View_Output "TRUE")
    (DRC_Report_File
       "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SPARTAN3_DDR1\ORCADSCHEMATICS\SPARTAN3_Rev5_030805.DRC")
    (BOM_Scope "0")
    (BOM_Mode "0")
    (BOM_Report_File
       "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SPARTAN3_DDR1\ORCADSCHEMATICS\SPARTAN3_REV6_031505.BOM")
    (BOM_Merge_Include "FALSE")
    (BOM_Property_Combine_7.0
       "{Item}\t{Quantity}\t{Reference}\t{Value}\t{PCB Footprint}")
    (BOM_Header "Item\tQuantity\tReference\tValue\tFootprint")
    (BOM_Include_File
       "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SPARTAN3_DDR1\ORCADSCHEMATICS\SPARTAN3_DDR1.INC")
    (BOM_Include_File_Combine_7.0 "{Item}\t{Quantity}\t{Reference}\t{Value}")
    (BOM_One_Part_Per_Line "FALSE")
    (BOM_View_Output "TRUE")
    ("Create Allegro Netlist" "TRUE")
    ("Allegro Netlist Directory"
       "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SPARTAN3_DDR1\ORCADSCHEMATICS")
    ("View Allegro Netlist Files" "TRUE")
    ("Update Allegro Board" "FALSE")
    ("Allegro Netlist Output Board File" "allegro\spartan3_ddr1.brd")
    ("Allegro Netlist Remove Etch" "FALSE")
    ("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
    ("Allegro Netlist Open Board in Allegro" "ALLEGRO")
    ("Allegro Setup Configuration File"
       "C:\Cadence\PSD_14.2\tools\capture\allegro.cfg")
    ("Allegro Setup Backup Versions" "3")
    (Netlist_TAB "0"))
  (Folder "Outputs"
    (File ".\spartan3_rev6_031505.bom"
      (Type "Report"))
    (File ".\pstxnet.dat"
      (Type "Report")
      (DisplayName "pstxnet.dat"))
    (File ".\pstxprt.dat"
      (Type "Report")
      (DisplayName "pstxprt.dat"))
    (File ".\pstchip.dat"
      (Type "Report")
      (DisplayName "pstchip.dat")))
  (Folder "Referenced Projects")
  (PartMRUSelector
    (RPAK_BUS18_50
      (FullPartName "RPAK_BUS18_50.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (CON_SMA_ST
      (FullPartName "CON_SMA_ST.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (TPS54872
      (FullPartName "TPS54872.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (TPS54310
      (FullPartName "TPS54310.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (OFFPAGELEFT-L
      (LibraryName "C:\CADENCE\PSD_14.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (TPS79633DCQ
      (FullPartName "TPS79633DCQ.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (TPS79601DCQ
      (FullPartName "TPS79601DCQ.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (VCC_BAR
      (LibraryName "C:\CADENCE\PSD_14.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (OFFPAGELEFT-R
      (LibraryName "C:\CADENCE\PSD_14.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (PORTRIGHT-L
      (LibraryName "C:\CADENCE\PSD_14.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (PORTRIGHT-R
      (LibraryName "C:\CADENCE\PSD_14.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (Si5475DC
      (FullPartName "Si5475DC.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (CAPACITOR_POL/SM
      (FullPartName "CAPACITOR_POL/SM.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (SODIMM_200_ECC
      (FullPartName "SODIMM_200_ECC.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (TPS75003
      (FullPartName "TPS75003.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (CAPACITOR_NON-POL
      (FullPartName "CAPACITOR_NON-POL.Normal")
      (LibraryName "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\LIBRARY1.OLB")
      (DeviceIndex "0"))
    ("SW DIP-3"
      (FullPartName "SW DIP-3.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (PTH05010Y-AH
      (FullPartName "PTH05010Y-AH.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (PTH05050Y_AH
      (FullPartName "PTH05050Y_AH.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (SPARTAN3_3S1500FG676
      (FullPartName "SPARTAN3_3S1500FG676C.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "2"))
    (PORTLEFT-R
      (LibraryName "C:\CADENCE\PSD_14.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (PORTBOTH-R
      (LibraryName "C:\CADENCE\PSD_14.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
      (DeviceIndex "0"))
    (PTH05010-WAH
      (FullPartName "PTH05010-WAH.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (PTH05000-WAH
      (FullPartName "PTH05000-WAH.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0"))
    (LT1764AEQ
      (FullPartName "LT1764AEQ.Normal")
      (LibraryName
         "C:\CADENCE_XILINX_PROJECTS\XILINX_PROJECTS\SERIALCACHE\LIBRARY1.OLB")
      (DeviceIndex "0")))
  (GlobalState
    (FileView
      (Path "Design Resources")
      (Path "Outputs")
      (Select "Design Resources"
         "C:\Cadence_Xilinx_Projects\Xilinx_Projects\Spartan3_DDR1\OrcadSchematics\spartan3_ddr1.dsn"))
    (HierarchyView)
    (Doc
      (Type "COrCapturePMDoc")
      (Frame
        (Placement "44 1 1 6 533 -4 -30 2 326 -1 493"))
      (Tab 0)))
  (LastUsedLibraryBrowseDirectory
     "C:\Cadence_Xilinx_Projects\Xilinx_Projects\SerialCache"))