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📄 pstxprt.dat

📁 fpga-sdram开发板-sch,本原理图是xilinx公司s3系列开发板的sdram
💻 DAT
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SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4619250@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4619250@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C230 'CAPACITOR NON-POL_0_DISCRETE_C0':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4117990@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4117990@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C231 'CAPACITOR NON-POL_0_DISCRETE_C0':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4118014@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4118014@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C232 'CAPACITOR NON-POL_0_DISCRETE_C0':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4118038@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4118038@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C233 'CAPACITOR NON-POL_0_DISCRETE_C0':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4118062@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4118062@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C237 'CAPACITOR POL_0_DISCRETE_C7343_':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4121755@V2P_QDR.CAPACITOR POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4121755@v2p_qdr.\capacitor pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C238 'CAPACITOR NON-POL_0_DISCRETE_C0':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4110438@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4110438@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C239 'CAPACITOR POL_0_DISCRETE_C7343_':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4121803@V2P_QDR.CAPACITOR POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4121803@v2p_qdr.\capacitor pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C24 'CAPACITOR NON-POL_0_DISCRETE_C0':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4623714@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4623714@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C240 'CAPACITOR POL_0_DISCRETE_C7343_':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4121827@V2P_QDR.CAPACITOR POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4121827@v2p_qdr.\capacitor pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C241 'CAPACITOR POL_0_DISCRETE_C7343_':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4121851@V2P_QDR.CAPACITOR POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4121851@v2p_qdr.\capacitor pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C25 'CAPACITOR NON-POL_0_DISCRETE_C0':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4624106@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4624106@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C251 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4712298@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4712298@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C252 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4712322@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4712322@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C253 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4712346@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4712346@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C254 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4712370@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4712370@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C255 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4712394@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4712394@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C256 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4712418@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4712418@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C257 'CAPACITOR NON-POL_0_DISCRETE__3':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4545261@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4545261@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C258 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4713336@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4713336@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C259 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4713360@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4713360@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C26 'CAPACITOR NON-POL_0_DISCRETE__2':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I3824167@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i3824167@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C260 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4713392@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4713392@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C261 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4714111@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4714111@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C262 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4714135@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4714135@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C263 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4714159@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4714159@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C264 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4714902@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4714902@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C265 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4714962@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4714962@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C266 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4714986@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4714986@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C267 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4715010@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4715010@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C269 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4715034@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4715034@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C27 'CAPACITOR NON-POL_0_DISCRETE__3':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4547475@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4547475@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C270 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4715058@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4715058@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C273 'CAPACITOR POL_0_DISCRETE_C7343_':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I3810735@V2P_QDR.CAPACITOR POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i3810735@v2p_qdr.\capacitor pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C276 'CAPACITOR NON-POL_0_DISCRETE__6':;SECTION_NUMBER 1 '@SPARTAN3_DDR1.SCHEMATIC1(SCH_1):POWER_IF@SPARTAN3_DDR1.POWER_IF(SCH_1):I4108696@V2P_QDR.CAPACITOR NON-POL_0.NORMAL(CHIPS)': C_PATH='@spartan3_ddr1.schematic1(sch_1):power_if@spartan3_ddr1.power_if(sch_1):i4108696@v2p_qdr.\capacitor non-pol_0.normal\(chips)', PRIM_FILE='.\pstchip.dat', SECTION='';PART_NAME C277 'CAPACITOR NON-POL_0_DISCRETE__5':;SECTION_NUMBER 1

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