4042.mdf

protel元件库

LISA MODEL DESCRIPTION FORMAT 6.0
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Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\CMOS SERIES MODEL DESIGNS\4042\4042.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  03/02/02
Modified: 09/02/04

*PROPERTIES,2    
TGQ=?
TGQB=?

*MAPPINGS,6,VALUE+VOLTAGE
4042+5V : TDLHCQ=225n, TDHLCQ=250n, TGQ=?, TDLHCQB= 250n, TDHLCQB=225n,  TGQB=?
4042+10V : TDLHCQ=100n, TDHLCQ=115n, TGQ=?,   TDLHCQB= 115n, TDHLCQB= 100n, TGQB=?
4042+15V : TDLHCQ=80n,   TDHLCQ=90n,   TGQ=?,   TDLHCQB= 90n,   TDHLCQB= 80n,   TGQB=?
CD4042+5V : TDLHCQ=225n, TDHLCQ=250n, TGQ=?, TDLHCQB= 250n, TDHLCQB=225n,  TGQB=?
CD4042+10V : TDLHCQ=100n, TDHLCQ=115n, TGQ=?,   TDLHCQB= 115n, TDHLCQB= 100n, TGQB=?
CD4042+15V : TDLHCQ=80n,   TDHLCQ=90n,   TGQ=?,   TDLHCQB= 90n,   TDHLCQB= 80n,   TGQB=?

*MODELDEFS,0    

*PARTLIST,7    
U1,DTFF,DTFF,PRIMITIVE=DIGITAL,TDHLCQ=<TDHLCQ>,TDHLCQB="<TDHLCQB> ",TDLHCQ=<TDLHCQ>,TDLHCQB=<TDLHCQB>,TGQ=<TGQ>,TGQB=<TGQB>
U2,DTFF,DTFF,PRIMITIVE=DIGITAL,TDHLCQ=<TDHLCQ>,TDHLCQB="<TDHLCQB> ",TDLHCQ=<TDLHCQ>,TDLHCQB=<TDLHCQB>,TGQ=<TGQ>,TGQB=<TGQB>
U3,DTFF,DTFF,PRIMITIVE=DIGITAL,TDHLCQ=<TDHLCQ>,TDHLCQB="<TDHLCQB> ",TDLHCQ=<TDLHCQ>,TDLHCQB=<TDLHCQB>,TGQ=<TGQ>,TGQB=<TGQB>
U4,DTFF,DTFF,PRIMITIVE=DIGITAL,TDHLCQ=<TDHLCQ>,TDHLCQB="<TDHLCQB> ",TDLHCQ=<TDLHCQ>,TDLHCQB=<TDLHCQB>,TGQ=<TGQ>,TGQB=<TGQB>
U5,OR_2,OR_2,PRIMITIVE=DIGITAL,TDHLDQ=30n,TDLHDQ=30n,TGQ=<TGQ>
U6,AND_2_D1_INV,AND_2_D1_INV,INVERT=D1,PRIMITIVE=DIGITAL,TDHLDQ=30n,TDLHDQ=30n,TGQ=<TGQ>
U7,AND_2_D1_INV,AND_2_D1_INV,INVERT=D1,PRIMITIVE=DIGITAL,TDHLDQ=30n,TDLHDQ=30n,TGQ=<TGQ>

*NETLIST,18   
#00000,5
U1,IP,CLK
U2,IP,CLK
U3,IP,CLK
U5,OP,Q
U4,IP,CLK

#00001,2
U5,IP,D0
U6,OP,Q

#00002,2
U5,IP,D1
U7,OP,Q

D0,2
D0,IT
U1,IP,D

Q0,2
Q0,OT
U1,OP,Q

$Q0$,2
$Q0$,OT
U1,OP,!Q

D1,2
D1,IT
U2,IP,D

Q1,2
Q1,OT
U2,OP,Q

$Q1$,2
$Q1$,OT
U2,OP,!Q

D2,2
D2,IT
U3,IP,D

Q2,2
Q2,OT
U3,OP,Q

$Q2$,2
$Q2$,OT
U3,OP,!Q

D3,2
D3,IT
U4,IP,D

Q3,2
Q3,OT
U4,OP,Q

$Q3$,2
$Q3$,OT
U4,OP,!Q

CLK,3
CLK,IT
U6,IP,D0
U7,IP,D1

POL,3
POL,IT
U6,IP,D1
U7,IP,D0

GND,9
GND,PR
U1,IP,RESET
U3,IP,SET
U3,IP,RESET
U4,IP,SET
U4,IP,RESET
U2,IP,RESET
U2,IP,SET
U1,IP,SET

*GATES,0