icm7212.mdf

protel元件库

LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\3RD PARTY LIBS_MODELS\VSM.LIBS SAMPLES\MOS CMOS LINEAR IC'S\ICM7212.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  19/10/03
Modified: 28/12/03

*PROPERTIES,0    

*MODELDEFS,0    

*PARTLIST,25   
E1,VCVS,1E6,PRIMITIVE=ANALOGUE
E2,VCVS,1E6,PRIMITIVE=ANALOGUE
M1,PMOSFET,PMOSFET,PRIMITIVE=ANALOGUE
M2,NMOSFET,NMOSFET,PRIMITIVE=ANALOGUE
M3,NMOSFET,NMOSFET,PRIMITIVE=ANALOGUE
M4,PMOSFET,PMOSFET,PRIMITIVE=ANALOGUE
M5,PMOSFET,PMOSFET,PRIMITIVE=ANALOGUE
M6,NMOSFET,NMOSFET,PRIMITIVE=ANALOGUE
M7,NMOSFET,NMOSFET,PRIMITIVE=ANALOGUE
R1,RESISTOR,1E6,PRIMITIVE=PASSIVE
R2,RESISTOR,1E6,PRIMITIVE=PASSIVE
R3,RESISTOR,50k,PRIMITIVE=ANALOGUE
R4,RESISTOR,86k,PRIMITIVE=ANALOGUE
R5,RESISTOR,50k,PRIMITIVE=ANALOGUE
U1,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U2,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U3,COUNTER_8,COUNTER_8,ALOAD=0,ARESET=0,INVERT="Q0,Q7",LOWER=0,PRIMITIVE=DIGITAL,RESET=0,UPPER=255,USEDIR=0
U4,NOR_2,NOR_2,PRIMITIVE=DIGITAL
U5,NOR_2,NOR_2,PRIMITIVE=DIGITAL
U6,NOR_2,NOR_2,PRIMITIVE=DIGITAL
U7,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U8,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U9,NAND_2,NAND_2,PRIMITIVE=DIGITAL
U10,NAND_2,NAND_2,INVERT=D0,PRIMITIVE=DIGITAL
U11,OR_2,OR_2,PRIMITIVE=DIGITAL

*NETLIST,36   
#00000,4
E1,PS,P
R1,PS,1
R4,PS,1
R3,PS,2

#00001,4
E2,PS,P
R2,PS,1
R5,PS,1
R4,PS,2

#00002,2
M1,PS,G
U2,OP,Q

#00003,3
M3,PS,D
U1,IP,D
M4,PS,G

#00004,2
U1,OP,Q
M7,PS,G

#00005,2
M4,PS,S
M5,PS,S

#00006,2
M6,PS,S
M7,PS,D

#00007,2
U3,OP,Q0
U7,IP,D

#00008,1
U3,OP,Q1

#00009,1
U3,OP,Q2

#00010,1
U3,OP,Q3

#00011,2
U3,IP,UCLK
U4,OP,Q

#00012,1
U3,IP,DCLK

#00013,1
U3,OP,MIN

#00014,1
U3,OP,MAX

#00015,1
U3,IP,CNTUP

#00016,1
U3,OP,RCO

#00017,1
U3,OP,Q4

#00018,1
U3,OP,Q5

#00019,1
U3,OP,Q6

#00020,2
U3,OP,Q7
U8,IP,D

#00021,2
U5,IP,D0
U6,OP,Q

#00022,2
U9,IP,D1
U11,OP,Q

RC,8
RC,GT
E1,PS,N
R1,PS,2
M3,PS,G
R2,PS,2
E2,PS,N
M1,PS,D
M2,PS,D

IO,4
IO,BT
M5,PS,D
M6,PS,D
U4,IP,D1

VDD,9
VDD,PR
U3,IP,OE
U3,IP,CE
M4,PS,D
M4,PS,B
M5,PS,B
M1,PS,S
R3,PS,1
M1,PS,B

VSS,12
VSS,PR
U3,IP,RESET
M6,PS,B
M7,PS,B
M7,PS,S
R5,PS,2
M2,PS,B
M2,PS,S
E1,PS,-
E2,PS,-
M3,PS,B
M3,PS,S

TRIG,2
TRIG,IT
U5,IP,D1

RESET,2
RESET,IT
U6,IP,D0

DIV2,2
DIV2,OT
U7,OP,Q

DIV128/256,2
DIV128/256,OT
U8,OP,Q

#00023,5
U9,IP,D0
U10,OP,Q
M2,PS,G
M5,PS,G
M6,PS,G

#00024,2
U9,OP,Q
U10,IP,D1

#00025,2
U10,IP,D0
E1,PS,+

#00026,14
U11,IP,D0
U2,IP,D
U4,IP,D0
U3,IP,D1
U3,IP,D2
U3,IP,D3
U3,IP,D4
U3,IP,D5
U3,IP,D6
U3,IP,D7
U3,IP,LOAD
U6,IP,D1
U5,OP,Q
U3,IP,D0

#00027,2
U11,IP,D1
E2,PS,+

*GATES,0