maxim240.mdf

protel元件库

LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\MICROCONTROLLERS\MAXIM\RS232\MAX240.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  23/08/04
Modified: 24/08/04

*PROPERTIES,2    
TDRX=500n
TDTX=1u

*MODELDEFS,0    

*PARTLIST,27   
BAT1,BATTERY,10V,PRIMITIVE=ANALOGUE
BAT2,BATTERY,10V,PRIMITIVE=ANALOGUE
R1,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R2,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R3,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R4,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R5,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R6,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R7,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R8,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R9,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R10,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R11,RES,1k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R12,RES,1M,PRIMITIVE=ANALOG,PRIMTYPE=RESISTOR
SW1,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=1,RON=1T,TSWITCH=1u
SW2,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=1,RON=1T,TSWITCH=1u
U1,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U2,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U3,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U4,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U5,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U6,TRIBUFFER,TRIBUFFER.DM,INVERT=Q,PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U7,TRIBUFFER,TRIBUFFER.DM,INVERT=Q,PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U8,TRIBUFFER,TRIBUFFER.DM,INVERT=Q,PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U9,TRIBUFFER,TRIBUFFER.DM,INVERT=Q,PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U10,TRIBUFFER,TRIBUFFER.DM,INVERT=Q,PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U11,AND_2,AND_2,INVERT="D1,D0",PRIMITIVE=DIGITAL

*NETLIST,30   
#00000,6
U6,IP,OE
U7,IP,OE
U8,IP,OE
U9,IP,OE
U10,IP,OE
U11,OP,Q

#00001,2
SW1,IO,A
BAT1,PS,-

#00002,2
SW2,IO,A
BAT2,PS,+

#00003,2
BAT1,PS,+
BAT2,PS,-

T1OUT,2
T1OUT,OT
U1,OP,Q

T2OUT,2
T2OUT,OT
U2,OP,Q

T3OUT,2
T3OUT,OT
U5,OP,Q

T4OUT,2
T4OUT,OT
U3,OP,Q

T1IN,3
T1IN,IT
R1,PS,1
U1,IP,D

T2IN,3
T2IN,IT
R2,PS,1
U2,IP,D

T3IN,3
T3IN,IT
R3,PS,1
U5,IP,D

T4IN,3
T4IN,IT
R4,PS,1
U3,IP,D

T5OUT,2
T5OUT,OT
U4,OP,Q

T5IN,3
T5IN,IT
R5,PS,1
U4,IP,D

SHDN,9
SHDN,IT
U1,IP,OE
U2,IP,OE
U5,IP,OE
U3,IP,OE
U4,IP,OE
U11,IP,D0
SW1,IP,EN
SW2,IP,EN

R1IN,3
R1IN,IT
U6,IP,D
R6,PS,2

R1OUT,2
R1OUT,OT
U6,OP,Q

R2IN,3
R2IN,IT
U7,IP,D
R7,PS,2

R2OUT,2
R2OUT,OT
U7,OP,Q

R3IN,3
R3IN,IT
U8,IP,D
R8,PS,2

R3OUT,2
R3OUT,OT
U8,OP,Q

R4IN,3
R4IN,IT
U9,IP,D
R9,PS,2

R4OUT,2
R4OUT,OT
U9,OP,Q

R5IN,3
R5IN,IT
U10,IP,D
R10,PS,2

R5OUT,2
R5OUT,OT
U10,OP,Q

$EN$,3
$EN$,IT
U11,IP,D1
R11,PS,1

C1-,4
C1-,GT
C2-,GT
VP-,GT
SW1,IO,B

GND,7
GND,PR
R12,PS,1
R6,PS,1
R9,PS,1
R10,PS,1
R8,PS,1
R7,PS,1

C1+,4
C1+,GT
C2+,GT
VP+,GT
SW2,IO,B

VCC,8
VCC,PR
R12,PS,2
R11,PS,2
R1,PS,2
R2,PS,2
R3,PS,2
R4,PS,2
R5,PS,2

*GATES,0