vcdream.mdf

protel元件库

LISA MODEL DESCRIPTION FORMAT 6.1
=================================
Design:   C:\Documents and Settings\ANYUSER\My Documents\ISIS PROJECTS\MIXED MODEL PROJECTS\SLDVDD_ISIS_AUTOMATION\ISIS LIBRARY PARTS AND MODELS DESIGNS AND TEST DESIGNS\SUB PARTS MODELS\VCDREAM.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  10/02/06
Modified: 10/12/06

*PROPERTIES,0    

*MODELDEFS,0    

*PARTLIST,5    
ADC1,ADC_8,ADC_8,INVERT=HOLD,MODDLL=DATAC,MODE=UNSIGNED,PRIMITIVE=PASSIVE,TDHLCD=1us,TDHZOD=1us,TDLHCD=1us,TDLZOD=1us,TDZHOE=1us,TDZLOE=1us,TG=1us
R1,RES,1000T,PRIMITIVE=ANALOG,PRIMTYPE=RESISTOR
U1,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U2,INVERTER,INVERTER,PRIMITIVE=DIGITAL
V1,VSOURCE,+256v,PRIMITIVE=ANALOG

*NETLIST,16   
#00000,2
ADC1,IP,VREF+
V1,PS,+

VIN,3
VIN,GT
ADC1,IP,VIN
R1,PS,1

GND,4
GND,PT
ADC1,IP,VREF-
R1,PS,2
V1,PS,-

DCLK,2
DCLK,GT
ADC1,IP,CLK

HOLDVIN,3
HOLDVIN,GT
ADC1,IP,HOLD
U2,IP,D

Q0,4
Q0,GT
CHB,GT
ADC1,OP,D0
U1,IP,D

Q1,2
Q1,GT
ADC1,OP,D1

Q2,2
Q2,GT
ADC1,OP,D2

Q3,2
Q3,GT
ADC1,OP,D3

Q4,2
Q4,GT
ADC1,OP,D4

Q5,2
Q5,GT
ADC1,OP,D5

Q6,2
Q6,GT
ADC1,OP,D6

Q7,2
Q7,GT
ADC1,OP,D7

CHA,2
CHA,GT
U1,OP,Q

READY,2
READY,GT
U2,OP,Q

VCC,2
VCC,PT
ADC1,IP,OE

*GATES,0