vcpotlog.mdf

protel元件库

LISA MODEL DESCRIPTION FORMAT 6.1
=================================
Design:   C:\Documents and Settings\ANYUSER\My Documents\ISIS PROJECTS\MIXED MODEL PROJECTS\SLDVDD_ISIS_AUTOMATION\ISIS LIBRARY PARTS AND MODELS DESIGNS AND TEST DESIGNS\SUB PARTS MODELS\VCPOTLOG.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  31/03/05
Modified: 13/07/06

*PROPERTIES,9    
ANTILOGTAPER=<ANTILOGTAPER>
AVSVOLTS=<AVSVOLTS>
AW_VOLTS=<AW_VOLTS>
BW_VOLTS=<BW_VOLTS>
GCPP=<GCPP>
GR=<GR>
LOGTAPER=<LOGTAPER>
POTVAL=<POTVAL>
RSPREAD=<RSPREAD>

*MODELDEFS,0    

*PARTLIST,10   
AVS1,AVS,"1.0*V(A,B)",PRIMITIVE=ANALOGUE
AVS2,AVS,"<AVSVOLTS>-V(A,B)",PRIMITIVE=ANALOGUE
C1,CAPACITOR,<GCPP>,PRIMITIVE=ANALOGUE
R1,RESISTOR,<RSPREAD>,PRIMITIVE=ANALOGUE
R2,RESISTOR,<GR>,PRIMITIVE=ANALOGUE
R3,RESISTOR,<GR>,PRIMITIVE=ANALOGUE
R4,RESISTOR,<GR>,PRIMITIVE=ANALOGUE
R5,RESISTOR,<POTVAL>/<LOGTAPER>,PRIMITIVE=ANALOGUE
S1,VCR,VCR,PRIMITIVE=ANALOGUE,ROFF=<POTVAL>,RON=1p,VOFF=0,VON=<BW_VOLTS>
S2,VCR,VCR,PRIMITIVE=ANALOGUE,ROFF=<POTVAL>,RON=1p,VOFF=0,VON=<AW_VOLTS>

*NETLIST,8    
#00000,2
S1,PS,P
AVS1,PS,+

#00001,2
S2,PS,P
AVS2,PS,+

B,3
B,GT
S1,PS,+
R4,PS,2

W,5
W,GT
S1,PS,-
S2,PS,-
R3,PS,2
R5,PS,2

A,4
A,GT
S2,PS,+
R2,PS,2
R5,PS,1

VC_IN,4
VC_IN,GT
AVS1,PS,A
AVS2,PS,A
R1,PS,2

AGND,5
AGND,GT
R2,PS,1
R3,PS,1
R4,PS,1
C1,PS,1

GND,9
GND,PT
C1,PS,2
S1,PS,N
AVS1,PS,-
AVS2,PS,-
AVS1,PS,B
AVS2,PS,B
R1,PS,1
S2,PS,N

*GATES,0