40161.mdf

protel元件库

LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Documents and Settings\nonuser\My Documents\vsm.libs\PROF DUMPS\VSM.LIBS SAMPLES\cmos models tests\40160_1_2_3\CD40160_1_2_3_BMS.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  08/06/03
Modified: 12/06/03

*PROPERTIES,0    

*MODELDEFS,0    

*PARTLIST,6    
U1,COUNTER_4,COUNTER_4,ALOAD=0,ARESET=1,INVERT=RESET,PRIMITIVE=DIGITAL,USEDIR=0
U2,OR_2,OR_2,PRIMITIVE=DIGITAL
U4,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U5,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U6,AND_3,AND_3,PRIMITIVE=DIGITAL
U7,INVERTER,INVERTER,PRIMITIVE=DIGITAL

*NETLIST,24   
#00000,1
U1,IP,DCLK

#00001,2
U1,IP,LOAD
U7,OP,Q

#00002,2
U1,OP,MIN
U2,IP,D1

#00003,2
U1,OP,MAX
U2,IP,D0

#00004,1
U1,IP,CNTUP

#00005,1
U1,OP,RCO

#00006,2
U2,OP,Q
U6,IP,D0

#00007,2
U4,OP,Q
U6,IP,D2

#00008,2
U5,OP,Q
U6,IP,D1

A,2
A,IT
U1,IP,D0

B,2
B,IT
U1,IP,D1

C,2
C,IT
U1,IP,D2

D,2
D,IT
U1,IP,D3

Q0,2
Q0,OT
U1,OP,Q0

Q1,2
Q1,OT
U1,OP,Q1

Q2,2
Q2,OT
U1,OP,Q2

Q3,2
Q3,OT
U1,OP,Q3

CLK,2
CLK,IT
U1,IP,UCLK

VCC,2
VCC,PR
U1,IP,OE

$LD$,3
$LD$,IT
U1,IP,CE
U7,IP,D

$MR$,2
$MR$,IT
U1,IP,RESET

ENP,2
ENP,IT
U5,IP,D

ENT,2
ENT,IT
U4,IP,D

RCO,2
RCO,OT
U6,OP,Q

*GATES,0