boot.s

来自「嵌入式系统」· S 代码 · 共 224 行

;/*-----------------------------------------------------------------------------
;@@@@
;@@@@ (Summary)	: system init program
;@@@@
;@@@@ (Comment)	: 
;@@@@
;@@@@ (Author)	: 
;@@@@
;@@@@ (History)	: Date 		Modifier	Comment
;@@@@
;@@@@ (RCS ID)	: $Header$
;@@@@
;-----------------------------------------------------------------------------*/


;// INCLUDE FILES

;// DEFINE WHICH FILE IS TO BE INCLUDED
;/*******************************************************************************
; Define
;*******************************************************************************/
APD_EBI_SET_ENABLE EQU 1
APD_SDRAM_SET_ENABLE EQU 1
APD_CACHE_SET_ENABLE EQU 1
			
;/*******************************************************************************
; Init 
;*******************************************************************************/
	AREA    Init, CODE, READONLY
	GET EBI.s
	GET SDRAM.s
	GET CACHE.s
	GET CPUip.h
	GET CPUsystem.h

	EXPORT __start
__start
;	EXPORT __main
;__main
	ENTRY

	 IF :DEF: ROM_AT_ADDRESS_ZERO
;// If the ROM is at address 0 this is just a sequence of branches
        B       CPU_Reset_Handler
      B       CPU_Undefined_Handler
        B       CPU_SWI_Handler
        B       CPU_Prefetch_Handler
        B       CPU_Abort_Handler
        NOP             ; Reserved vector
        B       CPU_IRQ_Handler
        B       CPU_FIQ_Handler
    ELSE
;// Otherwise we copy a sequence of LDR PC instructions over the vectors
;// (Note: We copy LDR PC instructions because branch instructions
;// could not simply be copied, the offset in the branch instruction
;// would have to be modified so that it branched into ROM. Also, a
;// branch instructions might not reach if the ROM is at an address
;// > 32M).
;///// for target board test


 ;      LDR 	R0,=0XFFFF4C00
  ;     MOV	R2,#0X00
   ;    STR	R2,[R0,#0X030]
    ;   STR	R2,[R0,#0X034]
     ;  MOV	R2,#0XFFFFFF
      ; STR	R2,[R0,#0X24]
       ;STR	R2,[R0,#0X28]
;///////////////////////////////////////       
       
        MOV     R8, #0
        ADR     R9, Vector_Init_Block
        LDMIA   R9!, {R0-R7}
        STMIA   R8!, {R0-R7}
        LDMIA   R9!, {R0-R7}
        STMIA   R8!, {R0-R7}

;// Now fall into the LDR PC, Reset_Addr instruction which will continue
;// execution at 'Reset_Handler'

Vector_Init_Block	
	
        LDR     PC, CPU_Reset_Addr
        LDR     PC, CPU_Undefined_Addr
        LDR     PC, CPU_SWI_Addr
        LDR     PC, CPU_Prefetch_Addr
        LDR     PC, CPU_Abort_Addr
        NOP
        LDR     PC, CPU_IRQ_Addr
        LDR     PC, CPU_FIQ_Addr

CPU_Reset_Addr      DCD     CPU_Reset_Handler
CPU_Undefined_Addr  DCD     CPU_Undefined_Handler
CPU_SWI_Addr        DCD     CPU_SWI_Handler
CPU_Prefetch_Addr   DCD     CPU_Prefetch_Handler
CPU_Abort_Addr      DCD     CPU_Abort_Handler
                		DCD     0       ; Reserved vector
CPU_IRQ_Addr        DCD     CPU_IRQ_Handler
CPU_FIQ_Addr        DCD     CPU_FIQ_Handler
  	ENDIF
   
   
CPU_Undefined_Handler
CPU_SWI_Handler
CPU_Prefetch_Handler
CPU_Abort_Handler
	
	IMPORT  C_int_handler
CPU_IRQ_Handler
	STMDB	sp!, {a1-v1, ip, lr}
	BL		C_int_handler
	LDMIA	sp!, {a1-v1, ip, lr}
	SUBS	pc, lr, #4
	
;		SUB		R14,R14,#4	
;		STMFD	R13!,{R12,R14}	;ADD OCT-10-2002
 ;   	MRS		R12,SPSR		;ADD OCT-10-2002
  ;  	STMFD	R13!,{R12}		;ADD OCT-10-2002
   ; 	STMFD	R13!,{R0-R11}	;ADD OCT-10-2002
	;	BL		C_int_handler
		
;		MRS		R12,CPSR
;		ORR		R12,R12,#0X080
;		MSR		CPSR_c,R12
	;	LDMFD	R13!,{R0-R12}	;ADD OCT-10-2002
	;	MSR		SPSR_cxsf,R12	;ADD OCT-10-2002
	;	LDMFD	R13!,{R12,PC}^	;ADD OCT-10-2002
	;	SUBS	PC,R14,#4		;0X18	;return from IRQ_Int

CPU_FIQ_Handler
    
;/*******************************************************************************
; Reset Handler
;*******************************************************************************/
CPU_Reset_Handler

;/*******************************************************************************
; PIO Register
;*******************************************************************************/
init

;/*******************************************************************************
; EBI Setting
;*******************************************************************************/
	IF (APD_EBI_SET_ENABLE = 1)
		APD_EBI_SETTING
	ENDIF

;/*******************************************************************************
; SDRAM Setting
;*******************************************************************************/
;	IF (APD_SDRAM_SET_ENABLE = 1)
 ;   		APD_SDRAM_SETTING
;	ENDIF

;/*******************************************************************************
; CACHE Setting
;*******************************************************************************/
	IF (APD_CACHE_SET_ENABLE = 1)
		APD_CACHE_SETTING
	ENDIF

;/*******************************************************************************
; Set Stack Pointer
;*******************************************************************************/
		; Enter FIQ mode and set up the FIQ stack pointer
        MOV     R0, #APD_CPU_Mode_FIQ
        MSR     CPSR_c, R0
        LDR     R13, =APD_CPU_STACK_FIQ

		; Enter IRQ mode and set up the IRQ stack pointer
        MOV     R0, #APD_CPU_Mode_IRQ
        MSR     CPSR_c, R0
        LDR     R13, =APD_CPU_STACK_IRQ

		; Enter SVC mode and set up the SVC stack pointer
        MOV     R0, #APD_CPU_Mode_SVC
        MSR     CPSR_c, R0
        LDR     R13, =APD_CPU_STACK_SVC
        
   		; Enter ABT mode and set up the ABT stack pointer
        MOV     R0, #APD_CPU_Mode_ABT
        MSR     CPSR_c, R0
        LDR     R13, =APD_CPU_STACK_ABT
        
		; Enter UND mode and set up the UND stack pointer
        MOV     R0, #APD_CPU_Mode_UND
        MSR     CPSR_c, R0
        LDR     R13, =APD_CPU_STACK_UND

		; Enter USR mode and set up the USR stack pointer
        MOV     R0, #APD_CPU_Mode_USR
        MSR     CPSR_c, R0
        LDR     R13, =APD_CPU_STACK_USR
        
        IMPORT  |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
        IMPORT  |Image$$RW$$Base|       ; Base of RAM to initialise
        IMPORT  |Image$$ZI$$Base|       ; Base and limit of area
        IMPORT  |Image$$ZI$$Limit|      ; to zero initialise

        LDR     r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
        LDR     r1, =|Image$$RW$$Base|  ; and RAM copy
        LDR     r3, =|Image$$ZI$$Base|  ; Zero init base => top of initialised data
        CMP     r0, r1                  ; Check that they are different
        BEQ     %F1
0       CMP     r1, r3                  ; Copy init data
        LDRCC   r2, [r0], #4
        STRCC   r2, [r1], #4
        BCC     %B0
1       LDR     r1, =|Image$$ZI$$Limit| ; Top of zero init segment
        MOV     r2, #0
2       CMP     r3, r1                  ; Zero init
        STRCC   r2, [r3], #4
        BCC     %B2

;/*******************************************************************************
; C Entry
;*******************************************************************************/
	;IMPORT  C_Entry
	;b	C_Entry
 	IMPORT __main
 	b	__main
   	END