sdram.s

来自「嵌入式系统」· S 代码 · 共 282 行

;/*-----------------------------------------------------------------------------
;@@@@
;@@@@ Copyright (c) 2000 Sharp Corporation All rights reserved.
;@@@@
;@@@@ (Summary)	: SDRAM Setting Program
;@@@@
;@@@@ (Comment)	: 
;@@@@
;@@@@ (Author)	: K.Misaki  
;@@@@
;@@@@ (History)	: Date 		Modifier	Comment
;@@@@
;@@@@ (RCS ID)	: $Header$
;@@@@
;-----------------------------------------------------------------------------*/
	GET SDRAMip.h
	GET SDRAMsystem.h

	MACRO
$label	APD_SDRAM_SETTING

     LDR r0, =APD_SDRAM_BASE;

    IF (APD_SDRAM0_E = APD_SDRAM_ENABLE):LOR:\
       (APD_SDRAM1_E = APD_SDRAM_ENABLE)
	
	    ;***************************************
	    ;	set SDRAM Timing 0 Registers
	    ;***************************************
	    ;*** Check SCE Value ***
	    IF ((APD_SDRAM_RIF >= APD_SDRAM_RIF_MIN):LAND:\
	        (APD_SDRAM_RIF <= APD_SDRAM_RIF_MAX))
	    ELSE
	         APD_SDRAM_RIF Error;
	    ENDIF
	
	    ;*** Check RCC Value ***
	    IF ((APD_SDRAM_RCC = APD_SDRAM_x4):LOR:\
	        (APD_SDRAM_RCC = APD_SDRAM_x8):LOR:\
	        (APD_SDRAM_RCC = APD_SDRAM_x16):LOR:\
	        (APD_SDRAM_RCC = APD_SDRAM_x32))
	    ELSE
	         APD_SDRAM_RCC Error;
	    ENDIF
	
	    LDR r1, =(((APD_SDRAM_RIF:SHL:APD_SDRAM_RIF_OFFSET)-1):OR:\
	              (APD_SDRAM_RCC:SHL:APD_SDRAM_RCC_OFFSET));
	    STR r1, [r0, #APD_SDRAM_TIMING0_OFFSET];
	
	    ;***************************************
	    ;	set SDRAM Timing 1 Registers
	    ;***************************************
	    ;*** Check tRP Value ***
	    IF ((APD_SDRAM_tRP >= APD_SDRAM_tRP_MIN):LAND:\
	        (APD_SDRAM_tRP <= APD_SDRAM_tRP_MAX))
	    ELSE
	         APD_SDRAM_tRP Error;
	    ENDIF
	
	    ;*** Check tRAS Value ***
	    IF ((APD_SDRAM_tRAS >= APD_SDRAM_tRAS_MIN):LAND:\
	        (APD_SDRAM_tRAS <= APD_SDRAM_tRAS_MAX))
	    ELSE
	         APD_SDRAM_tRAS Error;
	    ENDIF
	
	    ;*** Check tRCD Value ***
	    IF ((APD_SDRAM_tRCD >= APD_SDRAM_tRCD_MIN):LAND:\
	        (APD_SDRAM_tRCD <= APD_SDRAM_tRCD_MAX))
	    ELSE
	         APD_SDRAM_tRCD Error;
	    ENDIF
	
	    ;*** Check tRC Value ***
	    IF ((APD_SDRAM_tRC >= APD_SDRAM_tRC_MIN):LAND:\
	        (APD_SDRAM_tRC <= APD_SDRAM_tRC_MAX))
	    ELSE
	         APD_SDRAM_tRC Error;
	    ENDIF
		LDR r1, =APD_SDRAM_tRP_V:OR:APD_SDRAM_tRAS_V:OR:\
				 APD_SDRAM_tRCD_V:OR:APD_SDRAM_tRC_V
	    STR r1, [r0, #APD_SDRAM_TIMING1_OFFSET];
	
	    ;***************************************
	    ;	set SDRAM Timing 2 Registers
	    ;***************************************
	    ;*** Check tRP Value ***
	    IF ((APD_SDRAM_tXSR >= APD_SDRAM_tXSR_MIN):LAND:\
	        (APD_SDRAM_tXSR <= APD_SDRAM_tXSR_MAX))
	    ELSE
	         APD_SDRAM_tXSR Error;
	    ENDIF
	
	    ;*** Check CAL Value ***
	    IF ((APD_SDRAM_CAL >= APD_SDRAM_CAL_MIN):LAND:\
	        (APD_SDRAM_CAL <= APD_SDRAM_CAL_MAX))
	    ELSE
	         APD_SDRAM_CAL Error;
	    ENDIF
	
	    ;*** Check tWR Value ***
	    IF ((APD_SDRAM_tWR >= APD_SDRAM_tWR_MIN):LAND:\
	        (APD_SDRAM_tWR <= APD_SDRAM_tWR_MAX))
	    ELSE
	         APD_SDRAM_tWR Error;
	    ENDIF
	
	    LDR r1, =(((APD_SDRAM_tXSR-1):SHL:APD_SDRAM_tXSR_OFFSET):OR:\
	              ((APD_SDRAM_CAL-1):SHL:APD_SDRAM_CAL_OFFSET):OR:\
	              ((APD_SDRAM_tWR-1):SHL:APD_SDRAM_tWR_OFFSET))
	    STR r1, [r0, #APD_SDRAM_TIMING2_OFFSET];
    
	ENDIF

    IF (APD_SDRAM0_E = APD_SDRAM_ENABLE)
	    ;***************************************
	    ;	set SDRAM Discriptions 0 Registers
	    ;***************************************
	    ;*** Check EBW Value ***
		
		
	    IF ((APD_SDRAM0_EBW = APD_SDRAM_EBW16):LOR:\
	        (APD_SDRAM0_EBW = APD_SDRAM_EBW32):LOR:\
	        (APD_SDRAM0_EBW = APD_SDRAM_EBW8))
	    ELSE
	         APD_SDRAM0_EBW Error;
	    ENDIF
		

	    ;*** Check BAW Value ***
	    IF ((APD_SDRAM0_BAW = APD_SDRAM_BANK2):LOR:\
	        (APD_SDRAM0_BAW = APD_SDRAM_BANK4))
	    ELSE
	         APD_SDRAM0_BAW Error;
	    ENDIF
	
	    ;*** Check RAW Value ***
	    IF ((APD_SDRAM0_RAW >= APD_SDRAM_RAW_MIN):LAND:\
	        (APD_SDRAM0_RAW <= APD_SDRAM_RAW_MAX))
	    ELSE
	         APD_SDRAM0_RAW Error;
	    ENDIF
	
	    ;*** Check CAW Value ***
	    IF ((APD_SDRAM0_CAW >= APD_SDRAM_CAW_MIN):LAND:\
	        (APD_SDRAM0_CAW <= APD_SDRAM_CAW_MAX))
	    ELSE
	         APD_SDRAM0_CAW Error;
	    ENDIF
	
	    LDR r1, =((APD_SDRAM0_EBW:SHL:APD_SDRAM_EBW_OFFSET):OR:\
	              (APD_SDRAM0_BAW:SHL:APD_SDRAM_BAW_OFFSET):OR:\
	              ((APD_SDRAM0_RAW-11):SHL:APD_SDRAM_RAW_OFFSET):OR:\
	              ((APD_SDRAM0_CAW-8):SHL:APD_SDRAM_CAW_OFFSET))
	    STR r1, [r0, #APD_SDRAM_SDR0_OFFSET];
    ENDIF
    
    IF (APD_SDRAM1_E = APD_SDRAM_ENABLE)
	    ;***************************************
	    ;	set SDRAM Discriptions 1 Registers
	    ;***************************************
	    ;*** Check EBW Value ***
	    IF ((APD_SDRAM1_EBW = APD_SDRAM_EBW16):LOR:\
	        (APD_SDRAM1_EBW = APD_SDRAM_EBW32):LOR:\
	        (APD_SDRAM1_EBW = APD_SDRAM_EBW8))
	    ELSE
	         APD_SDRAM1_EBW Error;
	    ENDIF
	
	    ;*** Check BAW Value ***
	    IF ((APD_SDRAM1_BAW = APD_SDRAM_BANK2):LOR:\
	        (APD_SDRAM1_BAW = APD_SDRAM_BANK4))
	    ELSE
	         APD_SDRAM1_BAW Error;
	    ENDIF
	
	    ;*** Check RAW Value ***
	    IF ((APD_SDRAM1_RAW >= APD_SDRAM_RAW_MIN):LAND:\
	        (APD_SDRAM1_RAW <= APD_SDRAM_RAW_MAX))
	    ELSE
	         APD_SDRAM1_RAW Error;
	    ENDIF
	
	    ;*** Check CAW Value ***
	    IF ((APD_SDRAM1_CAW >= APD_SDRAM_CAW_MIN):LAND:\
	        (APD_SDRAM1_CAW <= APD_SDRAM_CAW_MAX))
	    ELSE
	         APD_SDRAM1_CAW Error;
	    ENDIF
	
	    LDR r1, =((APD_SDRAM1_EBW:SHL:APD_SDRAM_EBW_OFFSET):OR:\
	              (APD_SDRAM1_BAW:SHL:APD_SDRAM_BAW_OFFSET):OR:\
	              ((APD_SDRAM1_RAW-11):SHL:APD_SDRAM_RAW_OFFSET):OR:\
	              ((APD_SDRAM1_CAW-8):SHL:APD_SDRAM_CAW_OFFSET))
	    STR r1, [r0, #APD_SDRAM_SDR1_OFFSET];
    ENDIF
    
    ;***************************************
	;	set SDRAM Segment Map Registers 0 
    ;***************************************
    ;*** Check E Value ***
    IF ((APD_SDRAM0_E = APD_SDRAM_ENABLE):LOR:\
        (APD_SDRAM0_E = APD_SDRAM_DISABLE))
    ELSE
         APD_SDRAM0_E Error;
    ENDIF

    ;*** Check SIZE Value ***
    IF ((APD_SDRAM0_SIZE >= APD_SDRAM_SIZE_MIN):LAND:\
        (APD_SDRAM0_SIZE <= APD_SDRAM_SIZE_MAX))
    ELSE
         APD_SDRAM0_SIZE Error;
    ENDIF

    LDR r1, =((APD_SDRAM0_E:SHL:APD_SDRAM_E_OFFSET):OR:\
	          (APD_SDRAM0_START:AND:APD_SDRAM_START_VALID):OR:\
	          (APD_SDRAM0_SIZE:SHL:APD_SDRAM_SIZE_OFFSET));
	STR r1, [r0, #APD_SDRAM_SEG0_OFFSET];

    ;***************************************
	;	set SDRAM Segment Map Registers 1 
    ;***************************************
    ;*** Check E Value ***
    IF ((APD_SDRAM1_E = APD_SDRAM_ENABLE):LOR:\
        (APD_SDRAM1_E = APD_SDRAM_DISABLE))
    ELSE
         APD_SDRAM1_E Error;
    ENDIF

    ;*** Check SIZE Value ***
    IF ((APD_SDRAM1_SIZE >= APD_SDRAM_SIZE_MIN):LAND:\
        (APD_SDRAM1_SIZE <= APD_SDRAM_SIZE_MAX))
    ELSE
         APD_SDRAM1_SIZE Error;
    ENDIF

	LDR r1, =((APD_SDRAM1_E:SHL:APD_SDRAM_E_OFFSET):OR:\
	          (APD_SDRAM1_START:AND:APD_SDRAM_START_VALID):OR:\
	          (APD_SDRAM1_SIZE:SHL:APD_SDRAM_SIZE_OFFSET));
	STR r1, [r0, #APD_SDRAM_SEG1_OFFSET];

    ;***************************************
    ;	set SDRAM Control Registers
    ;***************************************
    ;*** Check SCE Value ***
    IF ((APD_SDRAM_SCE = APD_SDRAM_ENABLE):LOR:\
        (APD_SDRAM_SCE = APD_SDRAM_DISABLE))
    ELSE
         APD_SDRAM_SCE Error;
    ENDIF

    ;*** Check SRE Value ***
    IF ((APD_SDRAM_SRE = APD_SDRAM_CONTROLLER):LOR:\
        (APD_SDRAM_SRE = APD_SDRAM_SELF))
    ELSE
         APD_SDRAM_SRE Error;
    ENDIF

    ;*** Check PSE Value ***
    IF ((APD_SDRAM_PSE = APD_SDRAM_KEEP_ACTIVE):LOR:\
        (APD_SDRAM_PSE = APD_SDRAM_AUTO_DOWN))
    ELSE
         APD_SDRAM_PSE Error;
    ENDIF

    ;*** Check PME Value ***
    IF ((APD_SDRAM_PME = APD_SDRAM_ENABLE):LOR:\
        (APD_SDRAM_PME = APD_SDRAM_DISABLE))
    ELSE
         APD_SDRAM_PME Error;
    ENDIF

    LDR r1, =((APD_SDRAM_SCE:SHL:APD_SDRAM_SCE_OFFSET):OR:\
              (APD_SDRAM_SRE:SHL:APD_SDRAM_SRE_OFFSET):OR:\
              (APD_SDRAM_PSE:SHL:APD_SDRAM_PSE_OFFSET):OR:\
              (APD_SDRAM_PME:SHL:APD_SDRAM_PME_OFFSET));
    STR r1, [r0, #APD_SDRAM_CNTROL_OFFSET];
	
	MEND
	
	END