📄 dev_def.h
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/*-----------------------------------------------------------------------------@@@@ Copyright (c) 2001 Sharp Corporation All rights reserved.@@@@ (Summary) : Sharp LH7953x series register definitions header file@@@@ (Comment) : Define Address and Parameters of Each IPs@@@@ (Author) : Kazuko FUKUDA@@@@ (History) : 2001/1/16 Kazuko FUKUDA@@ 28/05/2001 Tan WK Version 2.0 Added LH79532 suppport@@ 27/08/2001 Teo LL Version 3.0 Added LH79533 suppport@@@@ (RCS ID) :@@-----------------------------------------------------------------------------*/#ifndef DEV_DEF_H#define DEV_DEF_H/*-----------------------------------------------------------------------------@@ LH79531, LH79532 and LH79533 Registers Address Definition@@ [Note]: ** are not inlcuded for LH79532/3 Registers Address Definition@@@@ ==============================================@@ |** 0xFFFF0000 | IrDA Controller |@@ ==============================================@@ |** 0xFFFF0400 | USB Controller |@@ ==============================================@@ | 0xFFFF0800 | DMA Controller |@@ ==============================================@@ |** 0xFFFF2800 | LCD - DMTN & HR-TFT |@@ ==============================================@@ | 0xFFFF2000 | LCD - STN & TFT |@@ ==============================================@@ | 0xFFFF4000 | UART |@@ ==============================================@@ | 0xFFFF4C00 | Programmable I/O |@@ ==============================================@@ | 0xFFFF5000 | PWM |@@ ==============================================@@ | 0xFFFF5400 | SPI Controller |@@ =============================================@@ | 0xFFFF5800 | Counter/Timer |@@ ==============================================@@ | 0xFFFF7000 | RTC |@@ ==============================================@@ | 0xFFFF7400 | Interrupt Controller |@@ ==============================================@@ | 0xFFFF7800 | Reset & Power Controller |@@ ==============================================@@ | 0xFFFF7C00 | PLL |@@ ==============================================@@ | 0xFFFF8000 | Watchdog |@@ ==============================================@@ | 0xFFFFC000 | SDRAM |@@ ==============================================--------------------------------------------------------------------------------*//*****************************************************************************//* Direct Memory Access Controller (DMAC) Base Address *//*****************************************************************************/#define APD_DMACBASE (unsigned long)0xFFFF0800/*****************************************************************************//* LCD Controller (LCDC) Base Address *//*****************************************************************************/#define APD_LCDCBASE (unsigned long)0xFFFF2000 /* LCDC *//*****************************************************************************//* Universal Asynchronous Receiver/Transmitters (UART) Base Address *//*****************************************************************************/#define APD_UARTBASE (unsigned long)0xFFFF4000/*****************************************************************************//* Programmable Input/Output (PIO) Base Address *//*****************************************************************************/#define APD_PIOBASE (unsigned long)0xFFFF4C00#define APD_PIOABASE (unsigned long)0xFFFF4C00#define APD_PIOBBASE (unsigned long)0xFFFF4C20#define APD_PIOCBASE (unsigned long)0xFFFF4C40#define APD_PIODBASE (unsigned long)0xFFFF4C60/*****************************************************************************//* PWM Base Address *//*****************************************************************************/#define APD_PWMBASE (unsigned long)0xFFFF5000/*****************************************************************************//* SSI Base Address *//*****************************************************************************/#define APD_SSIBASE (unsigned long)0xFFFF5400/*****************************************************************************//* Timer/Counter (CT) Base Address *//*****************************************************************************/#define APD_CTBASE (unsigned long)0xFFFF5800/*****************************************************************************//* Real Time Clock (RTC) Base Address *//*****************************************************************************/#define APD_RTCBASE (unsigned long)0xFFFF7000/*****************************************************************************//* RPC Base Address *//*****************************************************************************/#define APD_RPCBASE (unsigned long)0xFFFF7800/*****************************************************************************//* PLL Base Address *//*****************************************************************************/#define APD_PLLBASE (unsigned long)0xFFFF7C00/*****************************************************************************//* Watchdog Timer (WDT) Base Address *//*****************************************************************************/#define APD_WDTBASE (unsigned long)0xFFFF8000/*****************************************************************************//* Interrupt Controller (INTC) Base Address *//*****************************************************************************/#define APD_INTCBASE (unsigned long)0xFFFF7400#define APD_IRQBASE (unsigned long)0xFFFF7400#define APD_FIQBASE (unsigned long)0xFFFF7500/*****************************************************************************//* Main ASBCTL Base Address *//*****************************************************************************/#define APD_ASBBASE (unsigned long)0xFFFFA000/*****************************************************************************//* External bus interface (EBI) Base Address *//*****************************************************************************/#define APD_EBIBASE (unsigned long)0xFFFFA400/*****************************************************************************//* Memory protection unit & local SRAM & CACHE Base Address *//*****************************************************************************/#define APD_MPUBASE (unsigned long)0xFFFFAC00/*****************************************************************************//* SDRAM Base Address *//*****************************************************************************/#define APD_SDRAMCBASE (unsigned long)0xFFFFC000#ifdef LH79532#ifndef LH79532_LH79533#define LH79532_LH79533#endif#endif#ifdef LH79533#ifndef LH79532_LH79533#define LH79532_LH79533#endif#endif#endif /* APD_DEV_DEF */⌨️ 快捷键说明
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