cacheip.h

嵌入式系统

;/*-----------------------------------------------------------------------------
;@@@@
;@@@@ (Summary)	: Cache IP Level Setting File
;@@@@
;@@@@ (Comment)	:
;@@@@
;@@@@ (Author)	:
;@@@@
;@@@@ (History)	: Date 		Modifier	Comment
;@@@@
;@@@@ (RCS ID)	: $Header$
;@@@@
;-----------------------------------------------------------------------------*/
;********************************************************************
; Seg(0乣7)Start
;-------------------------------------------------------------------
; APD_CACHEx_START_OFFSET  		Start Reg Offset Address
;********************************************************************
APD_CACHE0_START_OFFSET		EQU 0x00
APD_CACHE1_START_OFFSET		EQU 0x04
APD_CACHE2_START_OFFSET		EQU 0x08
APD_CACHE3_START_OFFSET		EQU 0x0C
APD_CACHE4_START_OFFSET		EQU 0x10
APD_CACHE5_START_OFFSET		EQU 0x14
APD_CACHE6_START_OFFSET		EQU 0x18
APD_CACHE7_START_OFFSET		EQU 0x1C

APD_CACHE_START_VALID   	EQU 0xFFFFFC00
;********************************************************************
; Seg(0乣7)Size
;-------------------------------------------------------------------
; APD_CACHEx_SIZE_OFFSET   		Size Reg Offset Address
;********************************************************************
APD_CACHE0_SIZE_OFFSET		EQU 0x20
APD_CACHE1_SIZE_OFFSET		EQU 0x24
APD_CACHE2_SIZE_OFFSET		EQU 0x28
APD_CACHE3_SIZE_OFFSET		EQU 0x2C
APD_CACHE4_SIZE_OFFSET		EQU 0x30
APD_CACHE5_SIZE_OFFSET		EQU 0x34
APD_CACHE6_SIZE_OFFSET		EQU 0x38
APD_CACHE7_SIZE_OFFSET		EQU 0x3C

APD_CACHE_S0			EQU 0x00
APD_CACHE_S1K			EQU 0x01
APD_CACHE_S2K			EQU 0x02
APD_CACHE_S4K			EQU 0x03
APD_CACHE_S8K			EQU 0x04
APD_CACHE_S16K			EQU 0x05
APD_CACHE_S32K			EQU 0x06
APD_CACHE_S64K			EQU 0x07
APD_CACHE_S128K			EQU 0x08
APD_CACHE_S256K			EQU 0x09
APD_CACHE_S512K			EQU 0x0A
APD_CACHE_S1M			EQU 0x0B
APD_CACHE_S2M			EQU 0x0C
APD_CACHE_S4M			EQU 0x0D
APD_CACHE_S8M			EQU 0x0E
APD_CACHE_S16M			EQU 0x0F
APD_CACHE_S32M			EQU 0x10
APD_CACHE_S64M			EQU 0x11
APD_CACHE_S128M			EQU 0x12
APD_CACHE_S256M			EQU 0x13
APD_CACHE_S512M			EQU 0x14
APD_CACHE_S1G			EQU 0x15

APD_CACHE_SIZE_VALID		EQU 0x1F

;********************************************************************
; Seg(0乣7)Cfg
;-------------------------------------------------------------------
; APD_CACHEx_CFG_OFFSET   		Size Reg Offset Address
; APD_CACHE_DEF_OFFSET			Default Configration
;********************************************************************
APD_CACHE0_CFG_OFFSET		EQU 0x40
APD_CACHE1_CFG_OFFSET		EQU 0x44
APD_CACHE2_CFG_OFFSET		EQU 0x48
APD_CACHE3_CFG_OFFSET		EQU 0x4C
APD_CACHE4_CFG_OFFSET		EQU 0x50
APD_CACHE5_CFG_OFFSET		EQU 0x54
APD_CACHE6_CFG_OFFSET		EQU 0x58
APD_CACHE7_CFG_OFFSET		EQU 0x5C

APD_CACHE_DEF_OFFSET		EQU 0x60

APD_CACHE_SP_OFFSET  		EQU 4
APD_CACHE_NO			EQU 0x0
APD_CACHE_READ_ONLY		EQU 0x1
APD_CACHE_WRITE_ONLY		EQU 0x2
APD_CACHE_READ_WRITE		EQU 0x3

APD_CACHE_UP_OFFSET  		EQU 2

APD_CACHE_B_OFFSET  		EQU 1
APD_CACHE_NOT_BUFFERABLE	EQU 0x0
APD_CACHE_BUFFERABLE		EQU 0x1

APD_CACHE_C_OFFSET  		EQU 0
APD_CACHE_NOT_CACHEABLE		EQU 0x0
APD_CACHE_CACHEABLE		EQU 0x1
APD_CACHE_SM 			EQU 	0	;APD_CACHE_SRAM4KB
;********************************************************************
; SRAMTag :Local SRAM Start Address Register
;********************************************************************
APD_CACHE_S_START_OFFSET  	EQU	0x84

;********************************************************************
; CacheControlReg : Cache Control Register
;********************************************************************
APD_CACHE_CONTROL_OFFSET  	EQU	0x80

APD_CACHE_L_OFFSET		EQU 9
APD_CACHE_NO_LOCK		EQU 0
APD_CACHE_LOCK_LINE		EQU 1
APD_CACHE_LOCK_WRITE		EQU 2
APD_CACHE_LOCK_LINE_WRITE	EQU 3

APD_CACHE_BE_OFFSET     	EQU 8
APD_CACHE_LITTLE_ENDIAN		EQU 0
APD_CACHE_BIG_ENDIAN		EQU 1

APD_CACHE_W_OFFSET      	EQU 7
APD_CACHE_WB_DISABLE		EQU 0
APD_CACHE_WB_ENABLE		EQU 1

APD_CACHE_CM_OFFSET      	EQU 6
APD_CACHE_WRITE_BACK 		EQU 0
APD_CACHE_WRITE_THROUGH 	EQU 1

APD_CACHE_CE_OFFSET      	EQU 5
APD_CACHE_DISABLE	      	EQU 0
APD_CACHE_ENABLE	      	EQU 1

APD_CACHE_SE_OFFSET      	EQU 4
APD_CACHE_F_OFFSET      	EQU 3
APD_CACHE_I_OFFSET      	EQU 2

APD_CACHE_F 			EQU 0
APD_CACHE_I 			EQU 0
APD_CACHE_SM_OFFSET 		EQU 1
APD_CACHE_SRAM4KB		EQU 0
APD_CACHE_CACHE4KB		EQU 1
;********************************************************************
; CacheControlReg : Cache Control Register(for Long Name)
;********************************************************************
APD_CACHE_L_V	EQU APD_CACHE_L:SHL:APD_CACHE_L_OFFSET
APD_CACHE_BE_V	EQU APD_CACHE_BE:SHL:APD_CACHE_BE_OFFSET
APD_CACHE_W_V	EQU APD_CACHE_W:SHL:APD_CACHE_W_OFFSET
APD_CACHE_CM_V	EQU APD_CACHE_CM:SHL:APD_CACHE_CM_OFFSET
APD_CACHE_CE_E	EQU APD_CACHE_ENABLE:SHL:APD_CACHE_CE_OFFSET
APD_CACHE_CE_D	EQU APD_CACHE_DISABLE:SHL:APD_CACHE_CE_OFFSET
APD_CACHE_SE_E	EQU APD_CACHE_ENABLE:SHL:APD_CACHE_SE_OFFSET
APD_CACHE_SE_D	EQU APD_CACHE_DISABLE:SHL:APD_CACHE_SE_OFFSET
APD_CACHE_F_V   EQU APD_CACHE_F:SHL:APD_CACHE_F_OFFSET
APD_CACHE_I_V	EQU APD_CACHE_I:SHL:APD_CACHE_I_OFFSET
APD_CACHE_SM_V	EQU APD_CACHE_SM:SHL:APD_CACHE_SM_OFFSET

	END