sdramip.h

嵌入式系统

;/*-----------------------------------------------------------------------------
;@@@@
;@@@@ (Summary)	: SDRAM IP Level Setting File
;@@@@
;@@@@ (Comment)	:
;@@@@
;@@@@ (Author)	: 
;@@@@
;@@@@ (History)	: 
;@@@@
;@@@@ (RCS ID)	: $Header$
;@@@@
;-----------------------------------------------------------------------------*/

;********************************************************************
; APD_SDRAM_SEG_REGx_OFFSET		Segment Reg(0,1)Offset Address
;-------------------------------------------------------------------
; APD_SDRAM_E_OFFSET  			Enable Reg Offset Address
; APD_SDRAM_START_OFFSET  		Start Reg Offset Address
; APD_SDRAM_SIZE_OFFSET   		Size Reg Offset Address
;********************************************************************
APD_SDRAM_SEG0_OFFSET		EQU 0x00
APD_SDRAM_SEG1_OFFSET		EQU 0x08
APD_SDRAM_E_OFFSET  		EQU 31
APD_SDRAM_START_OFFSET  	EQU 13
APD_SDRAM_START_VALID   	EQU 0x3FFFE000
APD_SDRAM_SIZE_OFFSET   	EQU 0
APD_SDRAM_SIZE_MIN		EQU 0
APD_SDRAM_SIZE_MAX		EQU 0xF

;********************************************************************
; APD_SDRAM_SDR(0,1)_OFFSET  	Discriptions Reg Offset Address
;-------------------------------------------------------------------
; APD_SDRAM_SDR_EBW_OFFSET   	EBW Offset Bit
; APD_SDRAM_SDR_BAW_OFFSET     	BAW Offset Bit
; APD_SDRAM_SDR_RAW_OFFSET     	RAW Offset Bit
; APD_SDRAM_SDR_CAW_OFFSET     	CAW Offset Bit
;********************************************************************
APD_SDRAM_SDR0_OFFSET  		EQU	0x04
APD_SDRAM_SDR1_OFFSET  		EQU	0x0C

APD_SDRAM_EBW_OFFSET		EQU 0
APD_SDRAM_EBW8			EQU 4
APD_SDRAM_EBW16 		EQU 0
APD_SDRAM_EBW32			EQU 1

APD_SDRAM_BAW_OFFSET		EQU 1
APD_SDRAM_BANK2			EQU 0
APD_SDRAM_BANK4			EQU 1

APD_SDRAM_RAW_OFFSET		EQU 4
APD_SDRAM_RAW_MIN		EQU 11
APD_SDRAM_RAW_MAX		EQU 13

APD_SDRAM_CAW_OFFSET		EQU 8
APD_SDRAM_CAW_MIN		EQU 8
APD_SDRAM_CAW_MAX		EQU 11

;********************************************************************
; APD_SDRAM_CONTROL_OFFSET  	Segment Control Reg Offset Address
;-------------------------------------------------------------------
; APD_SDRAM_SCE_OFFSET   	SCE Offset Bit
; APD_SDRAM_SRE_OFFSET     	SRE Offset Bit
; APD_SDRAM_PSE_OFFSET     	PSE Offset Bit
; APD_SDRAM_PME_OFFSET     	PME Offset Bit
;********************************************************************
APD_SDRAM_CNTROL_OFFSET		EQU 0x10

APD_SDRAM_SCE_OFFSET		EQU	0

APD_SDRAM_SRE_OFFSET    	EQU	1
APD_SDRAM_CONTROLLER		EQU	0
APD_SDRAM_SELF			EQU	1

APD_SDRAM_PSE_OFFSET    	EQU 2
APD_SDRAM_KEEP_ACTIVE		EQU 0
APD_SDRAM_AUTO_DOWN		EQU 1

APD_SDRAM_PME_OFFSET    	EQU	3

;********************************************************************
; APD_SDRAM_STATUS_OFFSET  	Status Reg Offset Address
;-------------------------------------------------------------------
; APD_SDRAM_SCS_OFFSET   	SCS Offset Bit
; APD_SDRAM_SRS_OFFSET     	SRS Offset Bit
; APD_SDRAM_PSS_OFFSET     	PSS Offset Bit
;********************************************************************
APD_SDRAM_STATUS_OFFSET		EQU 0x14

APD_SDRAM_SCS_OFFSET   		EQU	0
APD_SDRAM_SRS_OFFSET     	EQU	1
APD_SDRAM_PSS_OFFSET     	EQU	2

;********************************************************************
; APD_SDRAM_TIMING0_OFFSET 	Timing 0 Reg Offset Address
;-------------------------------------------------------------------
; APD_SDRAM_RIF_OFFSET   	RIF Offset Bit
; APD_SDRAM_RCC_OFFSET     	RCC Offset Bit
;********************************************************************
APD_SDRAM_TIMING0_OFFSET	EQU 0x18

APD_SDRAM_RIF_OFFSET   		EQU	0
APD_SDRAM_RIF_MIN   		EQU	1
APD_SDRAM_RIF_MAX   		EQU	128

APD_SDRAM_RCC_OFFSET     	EQU 8
APD_SDRAM_x4			EQU 0x0
APD_SDRAM_x8			EQU 0x1
APD_SDRAM_x16			EQU 0x2
APD_SDRAM_x32			EQU 0x3

;********************************************************************
; APD_SDRAM_TIMING1_OFFSET 	Timing 1 Reg Offset Address
;-------------------------------------------------------------------
; APD_SDRAM_tRP_OFFSET   	tRP	 Offset Bit
; APD_SDRAM_tRAS_OFFSET     	tRAS Offset Bit
; APD_SDRAM_tRCD_OFFSET   	tRCD Offset Bit
; APD_SDRAM_tRC_OFFSET     	tRC  Offset Bit
;********************************************************************
APD_SDRAM_TIMING1_OFFSET	EQU 0x1C

APD_SDRAM_tRP_OFFSET   		EQU	0
APD_SDRAM_tRP_MIN	     	EQU 1
APD_SDRAM_tRP_MAX   	  	EQU 4

APD_SDRAM_tRAS_OFFSET     	EQU 8
APD_SDRAM_tRAS_MIN	     	EQU 1
APD_SDRAM_tRAS_MAX   	  	EQU 8

APD_SDRAM_tRCD_OFFSET   	EQU	16
APD_SDRAM_tRCD_MIN	     	EQU 1
APD_SDRAM_tRCD_MAX   	  	EQU 4

APD_SDRAM_tRC_OFFSET     	EQU 24
APD_SDRAM_tRC_MIN	     	EQU 1
APD_SDRAM_tRC_MAX   	  	EQU 16

; for long symbol
APD_SDRAM_tRP_V			EQU	(APD_SDRAM_tRP-1):SHL:APD_SDRAM_tRP_OFFSET
APD_SDRAM_tRAS_V		EQU (APD_SDRAM_tRAS-1):SHL:APD_SDRAM_tRAS_OFFSET
APD_SDRAM_tRCD_V		EQU	(APD_SDRAM_tRCD-1):SHL:APD_SDRAM_tRCD_OFFSET
APD_SDRAM_tRC_V			EQU (APD_SDRAM_tRC-1):SHL:APD_SDRAM_tRC_OFFSET

;********************************************************************
; APD_SDRAM_TIMING2_OFFSET 	Timing 2 Reg Offset Address
;-------------------------------------------------------------------
; APD_SDRAM_tXSR_OFFSET   	tXSR Offset Bit
; APD_SDRAM_CAL_OFFSET     	CAL	 Offset Bit
; APD_SDRAM_tWR_OFFSET   	tWR  Offset Bit
;********************************************************************
APD_SDRAM_TIMING2_OFFSET	EQU 0x20

APD_SDRAM_tXSR_OFFSET   	EQU	0
APD_SDRAM_tXSR_MIN		EQU	1
APD_SDRAM_tXSR_MAX   		EQU	16

APD_SDRAM_CAL_OFFSET     	EQU 8
APD_SDRAM_CAL_MIN	     	EQU 1
APD_SDRAM_CAL_MAX   	  	EQU 4

APD_SDRAM_tWR_OFFSET   		EQU	16
APD_SDRAM_tWR_MIN   		EQU	1
APD_SDRAM_tWR_MAX   		EQU	2

;********************************************************************
;setting value
;********************************************************************
APD_SDRAM_S8K     		EQU 0x0
APD_SDRAM_S16K			EQU 0x1
APD_SDRAM_S32K			EQU 0x2
APD_SDRAM_S64K			EQU 0x3
APD_SDRAM_S128K			EQU 0x4
APD_SDRAM_S256K			EQU 0x5
APD_SDRAM_S512K			EQU 0x6
APD_SDRAM_S1M     		EQU 0x7
APD_SDRAM_S2M     		EQU 0x8
APD_SDRAM_S4M     		EQU 0x9
APD_SDRAM_S8M     		EQU 0xA
APD_SDRAM_S16M			EQU 0xB
APD_SDRAM_S32M			EQU 0xC
APD_SDRAM_S64M			EQU 0xD
APD_SDRAM_S128M			EQU 0xE
APD_SDRAM_S256M			EQU 0xF

APD_SDRAM_ENABLE		EQU 1
APD_SDRAM_DISABLE		EQU 0
;********************************************************************
; APD_SDRAM_BASE      	Base Address
;********************************************************************
APD_SDRAM_BASE      		EQU 0xFFFFC000

	END