intc_def.h

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/*-----------------------------------------------------------------------------
@@
@@ (Summary)    : Interrupt Controller (INTC) IP Level Definitions 
@@		  Header File
@@
@@ (Comment)    : Define Registers of INTC
@@
@@ (Author)	: 
@@
@@ (History)	: 
@@
@@ (RCS ID)     :
@@
-----------------------------------------------------------------------------*/

#ifndef INTC_DEF_H
#define INTC_DEF_H

/* IRQ Register Addresses */
#define APD_INTCIRQSTATUS	((volatile APD_ULONG  *)(APD_IRQBASE ))		/* IRQ Status Register */
#define APD_INTCIRQRAWSTATUS	((volatile APD_ULONG  *)(APD_IRQBASE + 0x04))	/* IRQ Raw Status Register */
#define APD_INTCIRQENABLE	((volatile APD_ULONG  *)(APD_IRQBASE + 0x08))	/* IRQ Enable Register */
#define APD_INTCIRQENABLESET	((volatile APD_ULONG  *)(APD_IRQBASE + 0x08))	/* IRQ Enable Set Register */
#define APD_INTCIRQENABLECLEAR	((volatile APD_ULONG  *)(APD_IRQBASE + 0x0C))	/* IRQ Enable Clear Register */

/* FIQ Register Addresses */
#define APD_INTCFIQSTATUS	((volatile APD_ULONG  *)(APD_FIQBASE))		/* FIQ Status Register */
#define APD_INTCFIQRAWSTATUS	((volatile APD_ULONG  *)(APD_FIQBASE + 0x04))	/* FIQ Raw Status Register */
#define APD_INTCFIQENABLE	((volatile APD_ULONG  *)(APD_FIQBASE + 0x08))	/* FIQ Enable Register */
#define APD_INTCFIQENABLESET	((volatile APD_ULONG  *)(APD_FIQBASE + 0x08))	/* FIQ Enable Set Register */
#define APD_INTCFIQENABLECLEAR	((volatile APD_ULONG  *)(APD_FIQBASE + 0x0C))	/* FIQ Enable Clear Register */

/* INTC Configuration Register Addresses */
#define APD_INTCCONFIG0		((volatile APD_ULONG  *)(APD_INTCBASE + 0x200))	/* Configuration Register 0 */
#define APD_INTCCONFIG1		((volatile APD_ULONG  *)(APD_INTCBASE + 0x204))	/* Configuration Register 1 */
#define APD_INTCCLEAR		((volatile APD_ULONG  *)(APD_INTCBASE + 0x208))	/* Interrupt Clear Register */

/* Constant declarations for type of external device interrupt */

						/* config 0, config 1 */
#define APD_INTC_LOW_LEVEL_TRIG		0x00000000	/* Low-Level Trigger bit definition */
#define APD_INTC_HIGH_LEVEL_TRIG 	0x00001000	/* High-Level Trigger bit definition */
#define APD_INTC_FALL_EDGE_TRIG 	0x00100000	/* Falling-edge Trigger bit definition */
#define APD_INTC_RISE_EDGE_TRIG		0x00101000	/* Rising-edge Trigger bit definition */


/* Mask for setting INTC Configuration Registers */


#define APD_INTCCONFIG_MASK		0x0FF00000
#define APD_INTC_TRIG_OFST		0x8	

/* INTC Type Settings */
#define APD_INTC_INTTYPE	((APD_INTC_INT7TYPE << 7) | (APD_INTC_INT6TYPE << 6) | (APD_INTC_INT5TYPE << 5) | (APD_INTC_INT4TYPE << 4) | (APD_INTC_INT3TYPE << 3) | (APD_INTC_INT2TYPE << 2 ) | (APD_INTC_INT1TYPE << 1) | (APD_INTC_INT0TYPE)) 
#endif 	/* APD_INTC_DEF */