lcd_sys_def.h

嵌入式系统

/*-----------------------------------------------------------------------------
@@
@@ Copyright (c) 1998 Sharp Corporation All rights reserved.
@@
@@ (Summary)	: LCDC driver system define header file
@@
@@ (Comment)	: Define according to the system
@@
@@ (Author)		: Kazuko FUKUDA
@@
@@ (History)	: Date		Modifier	Comment
@@				2001/4/24	K.FUKUDA	BCD and PCD are moved from apd_lcd_def.h
@@
@@ (RCS ID)		: 
@@
-----------------------------------------------------------------------------*/
#ifndef APD_LCD_SYS_DEF
#define APD_LCD_SYS_DEF

#if !defined(APD_ARM_LEBO) && !defined(APD_ARM_BEBO)
#define	APD_ARM_LEBO
#endif

//#define	APD_LCD_VCI	0x02	//start of active video



//#define  CONFIG_PANEL_LQ057Q3DC02		//add nov/05/2002 xxgong

/* Define the bits per pixel */
#define APD_LCD_BPP	16
/* (Define one of the following value)
1	: 1 bit per pixel
2	: 2 bits per pixel
4	: 4 bits per pixel
8	: 8 bits per pixel
16	: 16 bits per pixel
*/

/* Define the Byte endian */
#define APD_LCD_LEBO
/* (Define one of the following value)
APD_LCD_LEBO	: Little Endian Byte Order
APD_LCD_BEBO	: Big Endian Byte Order
*/

/* Define the Pixel endian */
#define APD_LCD_LEPO
/* (Define one of the following value)
APD_LCD_LEPO	: Little Endian Pixel Order
APD_LCD_BEPO	: Big Endian Pixel Order
*/

/* Define the color data output */
#define APD_LCD_RGB
/* (Define one of the following value)
APD_LCD_RGB		: RGB Order Color Data Output
APD_LCD_BGR		: BGR Order Color Data Output
*/

/* For LH79532-EV, TFT, QVGA */
//#if (defined(CONFIG_PANEL_LQ057Q3DC02))

/* Define the type of LCD panel */
#define APD_LCD_SPSTN	//APD_LCD_TFT
/* (Define one of the following value)
APD_LCD_SPSTN	: single-panel STN
APD_LCD_DPSTN	: dual-panel STN
APD_LCD_TFT		: TFT
APD_LCD_HRTFT	: HR-TFT
APD_LCD_DMTN	: DMTN
*/

/* Define the detailed STN panel */
#define APD_LCD_COLOR_PANEL
/* (Define one of the following value if the panel is STN panel)
APD_LCD_MONO4_PANEL	: monochrome 8-bit interface
APD_LCD_MONO8_PANEL	: monochrome 4-bit interface
APD_LCD_COLOR_PANEL	: color STN
*/

/* Define the size of LCD panel */
#define APD_LCD_WIDTH		320	//320
#define APD_LCD_HEIGHT		240
/* (note)WIDTH must be a multiple of 16 */

/* Horizontal Back Porch [31:24] */
#define APD_LCD_HBP		0x05	//0x14
/* Horizontal Front Porch [23:16] */
#define APD_LCD_HFP		0x05	//0x14
/* Horizontal Sync Pulse Width [15:8] */
#define APD_LCD_HSW		0x0a	//0x28

/* Vertical Back Porch [31:24] */
#define APD_LCD_VBP		0x00	//0x04
/* Vertical Front Porch [23:16] */
#define APD_LCD_VFP		0	//0x0f
/* Vertical Sync Pulse Width [15:10] */
#define APD_LCD_VSW		0x0a  //0x03

/* Bypass Pixel Clock Divider (use for TFT)
  1: bypass, 0: not bypass */
#define APD_LCD_BCD		0

/* Pixel Clock Divider
   f(pixel_clk) = f(input_clk) / (2 + PCD) */
#define APD_LCD_PCD		22 /* 50MHz */

/* Control to Invert Output Enable [14] */
#define APD_LCD_IOE	0
/*
 0	: active high
 1	: active low
 */
/* Control to Invert Panel Clock [13] */
#define APD_LCD_IPC	0	//1 /* 1//0 */
/*
 0	: rise edge
 1	: fall edge
 */
/* Control to Invert Horizontal Sync [12] */
#define APD_LCD_IHS	0	//1
/*
 0	: active high
 1	: active low
 */
/* Control to Invert Vertical Sync [11] */
#define APD_LCD_IVS	0	//1
/*
 0	: active high
 1	: active low
 */
/* AC Bias frequency (valid only STN panel) [10:6] */
#define APD_LCD_ACB		0x00
/* Clock Select [5] */
#define APD_LCD_CLKSEL	0
/*
 0	: bus clock
 1	: external clock
 */

/* LCD Line End Enable [16] */
#define APD_LCD_LEE		0
/*
 0	: disable
 1	: enable
 */
/* Line End Delay [6:0] */
#define APD_LCD_LED		0x00
#if (defined(APD_LCD_HRTFT) || defined(APD_LCD_DMTN))
/* Horizontal Reverse Scan [2] (It only affects HR-TFT mode) */
#define APD_LCD_HRVE	1
/*
 0	: reverse scan
 1	: normal scan
 */
/* Vertical Reverse Scan [3] (It only affects HR-TFT mode) */
#define APD_LCD_VRVE	1
/*
 0	: reverse scan
 1	: normal scan
 */

/* Enables the SPS tristate output driver */
#define APD_LCD_SPSEN   0
/*
  0     : enable
  1     : disable
*/
/* Enables the CLS tristate output driver */
#define APD_LCD_CLSEN   0
/*
  0     : enable
  1     : disable
*/
/* Enables the LCD_UBL tristate output driver */
#define APD_LCD_UBLEN   0
/*
  0     : enable
  1     : disable
*/
/* Controls the DSPL_ENB output pin (It affects DMTN mode) */
#define APD_LCD_DISP   0
/* Contlor a general-purpose output enable */
#define APD_LCD_EN0    0
#define APD_LCD_EN1    0
#define APD_LCD_EN2    0
#define APD_LCD_EN3    0

/* Hsync-PS/CLS delay [11:8] (It affects HR-TFT or DMTN mode) */
#define APD_LCD_XDEL	0x08
/* Hsync-REV delay [7:4] (It affects HR-TFT or DMTN mode) */
#define APD_LCD_REVDEL	0x02
/* Hsync-LP time delay [3:0] (It affects HR-TFT or DMTN mode) */
#define APD_LCD_LPDEL	0x0d

/* SPL and SPR delays during vert front & back porches [15:9]
 (It affects HR-TFT or DMTN mode) */
#define APD_LCD_SPV	72
/* SPL-CLS and SPR-PS time delay [8:0] (It affects HR-TFT or DMTN mode) */
#define APD_LCD_XDEL2	288
#endif

//#endif

/* Set PIO */
//#define LH79532_PIO_LCD 0x7fff	//0x01FFFFFF

#endif /* APD_LCD_SYS_DEF */