cachesystem.h

嵌入式系统

;/*-----------------------------------------------------------------------------
;@@@@
;@@@@ Copyright (c) 2000 Sharp Corporation All rights reserved.
;@@@@
;@@@@ (Summary)	: Cache system Level Setting File
;@@@@
;@@@@ (Comment)	:
;@@@@
;@@@@ (Author)	: K.Misaki
;@@@@
;@@@@ (History)	: Date 		Modifier	Comment
;@@@@
;@@@@ (RCS ID)	: $Header$
;@@@@
;-----------------------------------------------------------------------------*/
;********************************************************************
; Cache and Local SRAM
; Please Setup APD_CACHEx_x Register
;
; Register              Value
;-------------------------------------------------------------------
; Protection Unit(SegXStart, SegXSize, SegXCfg Register)
;
; APD_CACHEx_START
; APD_CACHEx_SIZE 	(APD_CACHE_S0
;					 APD_CACHE_S1K,APD_CACHE_S2K,APD_CACHE_S4K,
;					 APD_CACHE_S8K,APD_CACHE_S16K,APD_CACHE_S32K,
;					 APD_CACHE_S64K,APD_CACHE_S128K,APD_CACHE_S256K,
;					 APD_CACHE_S512K,APD_CACHE_S1M,APD_CACHE_S2M,
;					 APD_CACHE_S4M,APD_CACHE_S8M,APD_CACHE_S16M,
;					 APD_CACHE_S32M,APD_CACHE_S64M,APD_CACHE_S128M,
;					 APD_CACHE_S256M,APD_CACHE_S512M,APD_CACHE_S1G)
; APD_CACHEx_SP   	(APD_CACHE_NO, APD_CACHE_READ_ONLY,
;					 APD_CACHE_WRITE_ONLY, APD_CACHE_READ_WRITE)
; APD_CACHEx_UP   	(APD_CACHE_NO, APD_CACHE_READ_ONLY,
;					 APD_CACHE_WRITE_ONLY, APD_CACHE_READ_WRITE)
; APD_CACHEx_B    	(APD_CACHE_NOT_BUFFERABLE or APD_CACHE_BUFFERABLE)
; APD_CACHEx_C    	(APD_CACHE_NOT_CACHEABLE or APD_CACHE_CACHEABLE)
;********************************************************************
;-Seg0Start, Seg0Size, Seg0Cfg Register------------------------------
APD_CACHE0_START	EQU 0x00000000
APD_CACHE0_SIZE 	EQU APD_CACHE_S1M
APD_CACHE0_SP   	EQU APD_CACHE_READ_WRITE
APD_CACHE0_UP   	EQU APD_CACHE_READ_WRITE
APD_CACHE0_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE0_C    	EQU APD_CACHE_NOT_CACHEABLE

;-Seg1Start, Seg1Size, Seg1Cfg Register------------------------------
APD_CACHE1_START	EQU 0x01000000
APD_CACHE1_SIZE 	EQU APD_CACHE_S8M
APD_CACHE1_SP   	EQU APD_CACHE_READ_WRITE
APD_CACHE1_UP   	EQU APD_CACHE_READ_WRITE
APD_CACHE1_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE1_C    	EQU APD_CACHE_NOT_CACHEABLE

;-Seg2Start, Seg2Size, Seg2Cfg Register------------------------------
APD_CACHE2_START	EQU 0x40000000
APD_CACHE2_SIZE 	EQU APD_CACHE_S16M
APD_CACHE2_SP   	EQU APD_CACHE_READ_WRITE
APD_CACHE2_UP   	EQU APD_CACHE_READ_WRITE
APD_CACHE2_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE2_C    	EQU APD_CACHE_NOT_CACHEABLE

;-Seg3Start, Seg3Size, Seg3Cfg Register------------------------------
APD_CACHE3_START	EQU 0x00000000
APD_CACHE3_SIZE 	EQU APD_CACHE_S0
APD_CACHE3_SP   	EQU APD_CACHE_NO
APD_CACHE3_UP   	EQU APD_CACHE_NO
APD_CACHE3_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE3_C    	EQU APD_CACHE_NOT_CACHEABLE

;-Seg4Start, Seg4Size, Seg4Cfg Register------------------------------
APD_CACHE4_START	EQU 0x00000000
APD_CACHE4_SIZE 	EQU APD_CACHE_S0
APD_CACHE4_SP   	EQU APD_CACHE_NO
APD_CACHE4_UP   	EQU APD_CACHE_NO
APD_CACHE4_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE4_C    	EQU APD_CACHE_NOT_CACHEABLE

;-Seg5Start, Seg5Size, Seg5Cfg Register------------------------------
APD_CACHE5_START	EQU 0x00000000
APD_CACHE5_SIZE 	EQU APD_CACHE_S0
APD_CACHE5_SP   	EQU APD_CACHE_NO
APD_CACHE5_UP   	EQU APD_CACHE_NO
APD_CACHE5_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE5_C    	EQU APD_CACHE_NOT_CACHEABLE

;-Seg6Start, Seg6Size, Seg6Cfg Register------------------------------
APD_CACHE6_START	EQU 0x00000000
APD_CACHE6_SIZE 	EQU APD_CACHE_S0
APD_CACHE6_SP   	EQU APD_CACHE_NO
APD_CACHE6_UP   	EQU APD_CACHE_NO
APD_CACHE6_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE6_C    	EQU APD_CACHE_NOT_CACHEABLE

;-Seg7Start, Seg7Size, Seg7Cfg Register------------------------------
APD_CACHE7_START	EQU 0x00000000
APD_CACHE7_SIZE 	EQU APD_CACHE_S0
APD_CACHE7_SP   	EQU APD_CACHE_NO
APD_CACHE7_UP   	EQU APD_CACHE_NO
APD_CACHE7_B    	EQU APD_CACHE_NOT_BUFFERABLE
APD_CACHE7_C    	EQU APD_CACHE_NOT_CACHEABLE

;********************************************************************
; SRAMTag:Local SRAM Start Address Register
;
; APD_CACHE_S_START  	(0x00000000乣)
;********************************************************************
APD_CACHE_S_START	EQU 0x00500000

;********************************************************************
; Cache Control Register
;
; APD_CACHE_L		(APD_CACHE_NO_LOCK, APD_CACHE_LOCK_LINE,
;                    APD_CACHE_LOCK_WRITE, APD_CACHE_LOCK_LINE_WRITE)
; APD_CACHE_BE     	(APD_CACHE_LITTLE_ENDIAN, APD_CACHE_BIG_ENDIAN)
; APD_CACHE_W      	(APD_CACHE_WB_DISABLE or APD_CACHE_WB_ENABLE)
; APD_CACHE_CM     	(APD_CACHE_WRITE_BACK or APD_CACHE_WRITE_THROUGH)
; APD_CACHE_CE     	depend on APD_CACHE_SM
; APD_CACHE_SE     	depend on APD_CACHE_SM
; APD_CACHE_F     	Not Used
; APD_CACHE_I     	Not Used
; APD_CACHE_SM   	(APD_CACHE_NOT_USED, APD_CACHE_SRAM8KB,
;					 APD_CACHE_CACHE8KB, APD_CACHE_SPLIT) - LH79531
; APD_CACHE_SM   	(APD_CACHE_SRAM4KB,APD_CACHE_CACHE4KB) - LH79532
;********************************************************************
APD_CACHE_L			EQU APD_CACHE_NO_LOCK
APD_CACHE_BE     	EQU APD_CACHE_LITTLE_ENDIAN
APD_CACHE_W      	EQU APD_CACHE_WB_ENABLE
APD_CACHE_CM      	EQU APD_CACHE_WRITE_BACK

	END