ebiip.h

嵌入式系统

;/*-----------------------------------------------------------------------------
;@@@@
;@@@@ Copyright (c) 2000 Sharp Corporation All rights reserved.
;@@@@
;@@@@ (Summary)	: EBI IP Level Setting File
;@@@@
;@@@@ (Comment)	:
;@@@@
;@@@@ (Author)	: K.Misaki
;@@@@
;@@@@ (History)	: Date 		Modifier	Comment
;@@@@
;@@@@ (RCS ID)	: $Header$
;@@@@
;-----------------------------------------------------------------------------*/
;********************************************************************
; APD_EBI_SEG_NUM           		Segment Number
;********************************************************************
APD_EBI_SEG_NUM           		EQU 7

;********************************************************************
; APD_RAM_SEG_REGx_OFFSET			Segment Reg(0-7)Offset Address
;-------------------------------------------------------------------
; APD_RAM_SEG_REG_E_OFFSET  		Enable Reg Offset Address
; APD_RAM_SEG_REG_START_OFFSET  	Start Reg Offset Address
; APD_RAM_SEG_REG_SIZE_OFFSET   	Size Reg Offset Address
;********************************************************************
APD_RAM_SEG_REG0_OFFSET			EQU 0x00
APD_RAM_SEG_REG1_OFFSET			EQU 0x04
APD_RAM_SEG_REG2_OFFSET			EQU 0x08
APD_RAM_SEG_REG3_OFFSET			EQU 0x0C
APD_RAM_SEG_REG4_OFFSET			EQU 0x10
APD_RAM_SEG_REG5_OFFSET			EQU 0x14
APD_RAM_SEG_REG6_OFFSET			EQU 0x18
APD_RAM_SEG_REG7_OFFSET			EQU 0x1C

APD_RAM_SEG_REG_E_OFFSET  		EQU 31

APD_RAM_SEG_REG_START_OFFSET    EQU 13
APD_RAM_SEG_REG_START_VALID     EQU 0x3FFFE000

APD_RAM_SEG_REG_SIZE_OFFSET     EQU 0
APD_EBI_S8K     EQU 0x0
APD_EBI_S16K	EQU 0x1
APD_EBI_S32K	EQU 0x2
APD_EBI_S64K	EQU 0x3
APD_EBI_S128K	EQU 0x4
APD_EBI_S256K	EQU 0x5
APD_EBI_S512K	EQU 0x6
APD_EBI_S1M     EQU 0x7
APD_EBI_S2M     EQU 0x8
APD_EBI_S4M     EQU 0x9
APD_EBI_S8M     EQU 0xA
APD_EBI_S16M	EQU 0xB
APD_EBI_S32M	EQU 0xC
APD_EBI_S64M	EQU 0xD
APD_EBI_SIZE_MIN	EQU APD_EBI_S8K
APD_EBI_SIZE_MAX	EQU APD_EBI_S64M

;********************************************************************
; APD_RAM_SEG_CTL(0乣7)_OFFSET  	Segment Control Reg Offset Address
;-------------------------------------------------------------------
; APD_RAM_SEG_CTL_IDLE_OFFSET   	Ctrl IDLE Offset Bit
; APD_RAM_SEG_CTL_RS_OFFSET     	Ctrl RS Offset Bit
; APD_RAM_SEG_CTL_RH_OFFSET     	Ctrl RH Offset Bit
; APD_RAM_SEG_CTL_WS_OFFSET     	Ctrl WS Offset Bit
; APD_RAM_SEG_CTL_WH_OFFSET     	Ctrl WH Offset Bit
; APD_RAM_SEG_CTL_AS_OFFSET     	Ctrl AS Offset Bit
; APD_RAM_SEG_CTL_AH_OFFSET     	Ctrl AH Offset Bit
; APD_RAM_SEG_CTL_P_OFFSET      	Ctrl P Offset Bit
; APD_RAM_SEG_CTL_S_OFFSET      	Ctrl S Offset Bit
; APD_RAM_SEG_CTL_N-SPEED_OFFSET 	Ctrl N-SPEED Offset Bit
; APD_RAM_SEG_CTL_S-SPEED_OFFSET 	Ctrl S-SPEED Offset Bit
;********************************************************************
APD_RAM_SEG_CTL0_OFFSET  		EQU	0x20
;for long symbol

APD_EBI0_IDLE_V	EQU	APD_EBI0_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI0_RS_V	EQU APD_EBI0_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI0_RH_V	EQU APD_EBI0_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI0_WS_V	EQU	APD_EBI0_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI0_WH_V	EQU APD_EBI0_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI0_AS_V	EQU APD_EBI0_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI0_AH_V	EQU APD_EBI0_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI0_P_V	EQU APD_EBI0_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI0_S_V	EQU APD_EBI0_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI0_NS_V 	EQU (((:NOT:APD_EBI0_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI0_SS_V	EQU (((:NOT:APD_EBI0_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI0_NSS_V	EQU APD_EBI0_NS_V:OR:APD_EBI0_SS_V

APD_RAM_SEG_CTL1_OFFSET  		EQU	0x24
;for long symbol
APD_EBI1_IDLE_V	EQU	APD_EBI1_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI1_RS_V	EQU APD_EBI1_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI1_RH_V	EQU APD_EBI1_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI1_WS_V	EQU	APD_EBI1_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI1_WH_V	EQU APD_EBI1_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI1_AS_V	EQU APD_EBI1_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI1_AH_V	EQU APD_EBI1_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI1_P_V	EQU APD_EBI1_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI1_S_V	EQU APD_EBI1_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI1_NS_V 	EQU (((:NOT:APD_EBI1_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI1_SS_V	EQU (((:NOT:APD_EBI1_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI1_NSS_V	EQU APD_EBI1_NS_V:OR:APD_EBI1_SS_V

APD_RAM_SEG_CTL2_OFFSET  		EQU	0x28
;for long symbol
APD_EBI2_IDLE_V	EQU	APD_EBI2_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI2_RS_V	EQU APD_EBI2_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI2_RH_V	EQU APD_EBI2_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI2_WS_V	EQU	APD_EBI2_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI2_WH_V	EQU APD_EBI2_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI2_AS_V	EQU APD_EBI2_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI2_AH_V	EQU APD_EBI2_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI2_P_V	EQU APD_EBI2_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI2_S_V	EQU APD_EBI2_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI2_NS_V 	EQU (((:NOT:APD_EBI2_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI2_SS_V	EQU (((:NOT:APD_EBI2_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI2_NSS_V	EQU APD_EBI2_NS_V:OR:APD_EBI2_SS_V

APD_RAM_SEG_CTL3_OFFSET  		EQU	0x2C
;for long symbol
APD_EBI3_IDLE_V	EQU	APD_EBI3_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI3_RS_V	EQU APD_EBI3_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI3_RH_V	EQU APD_EBI3_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI3_WS_V	EQU	APD_EBI3_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI3_WH_V	EQU APD_EBI3_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI3_AS_V	EQU APD_EBI3_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI3_AH_V	EQU APD_EBI3_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI3_P_V	EQU APD_EBI3_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI3_S_V	EQU APD_EBI3_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI3_NS_V 	EQU (((:NOT:APD_EBI3_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI3_SS_V	EQU (((:NOT:APD_EBI3_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI3_NSS_V	EQU APD_EBI3_NS_V:OR:APD_EBI3_SS_V

APD_RAM_SEG_CTL4_OFFSET  		EQU	0x30
;for long symbol
APD_EBI4_IDLE_V	EQU	APD_EBI4_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI4_RS_V	EQU APD_EBI4_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI4_RH_V	EQU APD_EBI4_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI4_WS_V	EQU	APD_EBI4_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI4_WH_V	EQU APD_EBI4_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI4_AS_V	EQU APD_EBI4_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI4_AH_V	EQU APD_EBI4_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI4_P_V	EQU APD_EBI4_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI4_S_V	EQU APD_EBI4_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI4_NS_V 	EQU (((:NOT:APD_EBI4_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI4_SS_V	EQU (((:NOT:APD_EBI4_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI4_NSS_V	EQU APD_EBI4_NS_V:OR:APD_EBI4_SS_V

APD_RAM_SEG_CTL5_OFFSET  		EQU	0x34
;for long symbol
APD_EBI5_IDLE_V	EQU	APD_EBI5_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI5_RS_V	EQU APD_EBI5_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI5_RH_V	EQU APD_EBI5_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI5_WS_V	EQU	APD_EBI5_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI5_WH_V	EQU APD_EBI5_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI5_AS_V	EQU APD_EBI5_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI5_AH_V	EQU APD_EBI5_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI5_P_V	EQU APD_EBI5_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI5_S_V	EQU APD_EBI5_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI5_NS_V 	EQU (((:NOT:APD_EBI5_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI5_SS_V	EQU (((:NOT:APD_EBI5_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI5_NSS_V	EQU APD_EBI5_NS_V:OR:APD_EBI5_SS_V

APD_RAM_SEG_CTL6_OFFSET  		EQU	0x38
;for long symbol
APD_EBI6_IDLE_V	EQU	APD_EBI6_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI6_RS_V	EQU APD_EBI6_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI6_RH_V	EQU APD_EBI6_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI6_WS_V	EQU	APD_EBI6_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI6_WH_V	EQU APD_EBI6_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI6_AS_V	EQU APD_EBI6_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI6_AH_V	EQU APD_EBI6_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI6_P_V	EQU APD_EBI6_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI6_S_V	EQU APD_EBI6_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI6_NS_V 	EQU (((:NOT:APD_EBI6_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI6_SS_V	EQU (((:NOT:APD_EBI6_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI6_NSS_V	EQU APD_EBI6_NS_V:OR:APD_EBI6_SS_V

APD_RAM_SEG_CTL7_OFFSET  		EQU	0x3C
;for long symbol
APD_EBI7_IDLE_V	EQU	APD_EBI7_IDLE:SHL:APD_RAM_SEG_CTL_IDLE_OFFSET
APD_EBI7_RS_V	EQU APD_EBI7_RS:SHL:APD_RAM_SEG_CTL_RS_OFFSET
APD_EBI7_RH_V	EQU APD_EBI7_RH:SHL:APD_RAM_SEG_CTL_RH_OFFSET
APD_EBI7_WS_V	EQU	APD_EBI7_WS:SHL:APD_RAM_SEG_CTL_WS_OFFSET
APD_EBI7_WH_V	EQU APD_EBI7_WH:SHL:APD_RAM_SEG_CTL_WH_OFFSET
APD_EBI7_AS_V	EQU APD_EBI7_AS:SHL:APD_RAM_SEG_CTL_AS_OFFSET
APD_EBI7_AH_V	EQU APD_EBI7_AH:SHL:APD_RAM_SEG_CTL_AH_OFFSET
APD_EBI7_P_V	EQU APD_EBI7_P:SHL:APD_RAM_SEG_CTL_P_OFFSET
APD_EBI7_S_V	EQU APD_EBI7_S:SHL:APD_RAM_SEG_CTL_S_OFFSET
APD_EBI7_NS_V 	EQU (((:NOT:APD_EBI7_NSPEED)+1):AND:APD_EBI_NSPEED_MASK):SHL:APD_RAM_SEG_CTL_NSPEED_OFFSET
APD_EBI7_SS_V	EQU (((:NOT:APD_EBI7_SSPEED)+1):AND:APD_EBI_SSPEED_MASK):SHL:APD_RAM_SEG_CTL_SSPEED_OFFSET
APD_EBI7_NSS_V	EQU APD_EBI7_NS_V:OR:APD_EBI7_SS_V

APD_RAM_SEG_CTL_IDLE_OFFSET		EQU 19
APD_EBI_IDLE_MIN				EQU 0
APD_EBI_IDLE_MAX				EQU 8

APD_RAM_SEG_CTL_RS_OFFSET		EQU 18
APD_RAM_SEG_CTL_RH_OFFSET     	EQU 17
APD_RAM_SEG_CTL_WS_OFFSET		EQU 16
APD_RAM_SEG_CTL_WH_OFFSET		EQU 15
APD_RAM_SEG_CTL_AS_OFFSET		EQU 14
APD_RAM_SEG_CTL_AH_OFFSET		EQU 13
APD_RAM_SEG_CTL_P_OFFSET		EQU 12
APD_RAM_SEG_CTL_S_OFFSET		EQU 10
APD_RAM_SEG_CTL_NSPEED_OFFSET	EQU 5
APD_RAM_SEG_CTL_SSPEED_OFFSET	EQU 0
APD_EBI_NSPEED_MIN              EQU 2
APD_EBI_NSPEED_MAX              EQU 32
APD_EBI_SSPEED_MIN              EQU 1
APD_EBI_SSPEED_MAX              EQU 32
APD_EBI_NSPEED_MASK				EQU 0x1F
APD_EBI_SSPEED_MASK				EQU 0x1F

;********************************************************************
; APD_RAM_EXTBIF_OFFSET		EXTBIF Ctrl Reg Offset Address
;-------------------------------------------------------------------
; APD_RAM_EXTBIF_Z              	EXTBIF Z Offset Bit
;********************************************************************
APD_RAM_EXTBIF_OFFSET			EQU 0x40
APD_RAM_EXTBIF_Z              	EQU 0

;********************************************************************
;setting value
;********************************************************************
APD_EBI_ENABLE	EQU 1
APD_EBI_DISABLE	EQU 0
APD_EBI_AFTER	EQU 0
APD_EBI_BEFORE  EQU 0
APD_EBI_SAME	EQU 1
APD_EBI_WORD4_PAGE	EQU 0
APD_EBI_WORD8_PAGE	EQU 1
APD_EBI_OUTPUT	EQU 0
APD_EBI_HIGH_Z	EQU 1

APD_EBI_BIT8 	EQU 0
APD_EBI_BIT16	EQU 1
APD_EBI_BIT32	EQU 2
;********************************************************************
; APD_EBI_BASE      	Base Address 
;********************************************************************
APD_EBI_BASE      		EQU 0xFFFFA400
	END
	END