saa7111.h

视频601芯片的驱动源码,你可以完全掌控该芯片了,对于其它多媒体芯片的设计具有参考价值

/*------------------------------------------------------------------------

$Workfile: SAA7111.H $
$Date: 8/07/96 1:29p $
$Revision: 7 $
* Purpose:	
*			Header for SAA7111 Video Input Processor Chip			
* Notes:       
*
$History: SAA7111.H $
 * 
 * *****************  Version 7  *****************
 * User: Dstarr       Date: 8/07/96    Time: 1:29p
 * Updated in $/601cman
 * Support Phillips mode
 * 
 * *****************  Version 6  *****************
 * User: Stevel       Date: 7/29/96    Time: 5:00p
 * Updated in $/601cman
 * rename HPLL_ON to HPLL_OPEN and delete HPLL_OFF.
 * 
 * *****************  Version 5  *****************
 * User: Dstarr       Date: 4/12/96    Time: 11:58a
 * Updated in $/601cman
 * Tristate SAA7111 in playback
 * 
 * *****************  Version 4  *****************
 * User: Dstarr       Date: 3/13/96    Time: 5:12p
 * Updated in $/601cman
 * Checked out in lab.  601test plays beauty thru dll.  Added pragma to
 * surpress "inconsistant use of dllimport, export assumed" warning.
 * 
 * *****************  Version 3  *****************
 * User: Dstarr       Date: 3/12/96    Time: 3:41p
 * Updated in $/601cman
 * Add declspec(dllexport) to the initial values structure so the diag
 * nostic can check that initial values did stick in  the registers.
 * 
 * *****************  Version 2  *****************
 * User: Stevel       Date: 3/10/96    Time: 10:05p
 * Updated in $/601cman
 * 
 * *****************  Version 1  *****************
 * User: Stevel       Date: 3/06/96    Time: 7:55p
 * Created in $/601cman
 * Initial release

  
    This code and information is provided "as is" without warranty of any
    kind, either expressed or implied, including but not limited to the
    implied warranties of merchantability and/or fitness for a particular
    purpose.
  
    1996 Analog Devices, Inc. 
  
-------------------------------------------------------------------------*/
#include "globsym.h"

#define LINKTODLL __declspec(dllimport)

//  Structure defined for Philips SAA 7111  registers
typedef struct	tagSAA7111
{
	byte	chipaddr;
	byte	subaddr;
	word	version;	// Chip name and version (R).
	byte	aico1;		// Input analog video control (R/W) Reg1
	byte	aico2;		// Input analog video control (R/W) Reg2
	byte	aico3;		// Channel 1 gain control (R/W) Reg.
	byte	aico4;		// Channel 2 gain control (R/W) Reg.
	byte	hsync_begin;// Horizontal Sync Begin (R/W) Reg.
	byte	hsync_stop;	// Horizontal Sync Stop (R/W) Reg.
	byte	sync_ctl;	// Sync. Control (R/W) Reg.
	byte	luma_ctl;	// Luma Control (R/W) Reg.
	byte	luma_brig;	// Luma Brightness Control (R/W) Reg.
	byte	luma_cont;	// Luma Contrast Control (R/W) Reg.
	byte	chroma_sat;	// Chroma Saturation Control Reg.
	byte	chroma_hue;	// Chroma Hue Control (R/W) Reg.
	byte	chroma_ctl;	// Chroma Control (R/W)	Reg.
	byte	reserve1;	// Reserve
	byte	format_delay;// Video out Format/Delay Ctl(R/W)Reg.
	byte	out_ctl1;	// Video Output Control (R/W) Reg.
	byte	out_ctl2;	// Video Output Control (R/W) Reg.
	byte	reserve[11];// reserved bytes
	byte	status;		// Status (R) Reg.
} SAA7111_REG;

#define CHROMACTL       0xE /* Register Number  */

#define	ALL7111REGS (sizeof(SAA7111_REG) - 2)
#define	ADCADDRESS	0x48

LINKTODLL SAA7111_REG	init_7111;/* Structure to hold initial values

/* aico1  control bits	*/

	/*  Composite Video input mux settings	*/

#define	COMP_VID_A11	0	/* Video input mux in A11 out AD1 */
#define	COMP_VID_A12	1	/* Video input mux in A12 out AD1 */
#define	COMP_VID_A21	2	/* Video input mux in A21 out AD2 */
#define	COMP_VID_A22	3	/* Video input mux in A22 out AD2 */

	/*  S-Video (separate Luma & Chroma Video input mux settings  */

#define	SVID_AGC_A1		4	/* Video input mux in A21-A11 	*/
#define	SVID_AGC_A2		5	/* Video input mux in A12-A22 		*/
#define	SVID_FIX_A1		6	/* Video input mux in A21-A11 		*/
#define	SVID_FIX_A2		7	/* Video input mux in A22-A21 		*/

	/* AGC update Hysterisis codes   */

#define	JERKY 			0		
#define	SMOOTH 			0x20
#define	SLUGGISH		0x38

	/* Front end bypass MUX settings		*/

#define	FRONTEND_ACTIVE	0xC0
#define	BYPASS_FRONTEND	0
#define	BYPASS_ANTIALIAS 0x80


/* sync control register bits			*/

#define	VNOI_NORMAL	0		/* Vertical Noise Reduction Normal mode */
#define	VNOI_OFF	3		/* Vertical Noise Reduction off */

#define	HPLL_OPEN	0x04  	/* Opens Horizontal Phase Lock Loop for playback */

#define	VTRC        8		/* Video Tape Recoder Mode. 0 == TV mode  */
#define FSEL        0x40	/* 1 = 525L & 60F(NTSC),0 = 625L & 50F (PAL) */
#define	AUFD        0x80	/* automatic 50/60 hz field rate selection*/

/* Luma Control Register Bits  */

#define UPTCV	4			/* 1 = Update AGC once per field 0 = once per line*/
#define PREF	0x40		/* 1 = Prefilter ON	*/
#define BYPS	0x80		/* 1 = Chroma trap filter OFF */	

	/* Band pass filter center frequencies		*/

#define BANDPASS4_1MHZ 	0	
#define BANDPASS3_8MHZ	0x10
#define BANDPASS2_6MHZ	0x20
#define	BANDPASS2_9MHZ	0x30

/* Luma Brightness codes	*/

#define CCIR_BRIG		0x80
#define	REALLY_BRIGHT	0xFF 


/* Luma Contrast Codes   */

#define	CCIR_CONTRAST	0x47
#define	MAX_CONTRAST	0x7F

/*  Chroma Saturation Codes    */

#define	CCIR_SAT		0x40
#define	MAX_SAT			0x7F

/* Chroma Control bits */

	/* Chroma Band Width		*/

#define	NARROW_BAND		0			/* 620 Khz  */
#define NOMINAL_BAND	1			/* 800 Khz  */
#define	MEDIUM_BAND		2			/* 920 Khz	*/
#define	WIDE_BAND		3			/* 1000Khz	*/

#define	FCTC			4			/* Fast Color Time Constant  */
#define	DCCF			8			/* Disable Chroma Comb Filter */
#define	RTCO_ON			0x40		/* enable RTCO output */
#define	CDTO			0x80		/* reset color burst phase */

/* Format Delay Control Register bits  */

	/* Output format select codes */

#define RGB565			0	
#define YUV422_16BIT	0x40	
#define YUV411_12BIT	0x80	
#define	YUV_CCIR656_8BIT 0xC0	



/* Output Control Register 1 bits	*/

#define	OEHV			4			/* Output Enable H & V Sync */
#define	OEYC			8			/* Output Enable Y and C	*/
#define TRI_STATE       0x80        /* Tri state data bus for playback */
   
/* Output Control Register 2 bits */

#define	AOUT_COMPOSITE	2			/* composite video on AOUT test pin */ 
#define	AOUT_LUMA		3			/* LUMA or feedback test video */




/*	Declare functions		*/

LINKTODLL int adc_init(int video_format, int direction
             ,int input_video, int vcr_mode, AMCC_OP_REGS * ptr2amcc_opregs);

LINKTODLL int read_adc_all_regs(SAA7111_REG * p7111Regs
                                , AMCC_OP_REGS * ptr2amcc_opregs);
LINKTODLL int write_adc_all_regs(SAA7111_REG * p7111Regs
                                 , AMCC_OP_REGS * ptr2amcc_opregs);
LINKTODLL int read_adc_reg(int SubAdr, byte * pVal
                           , AMCC_OP_REGS * ptr2amcc_opregs);
LINKTODLL int write_adc_reg(int SubAdr, byte Val
                            , AMCC_OP_REGS * ptr2amcc_opregs);