adv601.c

视频601芯片的驱动源码,你可以完全掌控该芯片了,对于其它多媒体芯片的设计具有参考价值

        init_601.mode_ctl |= ENCODE_601;


    init_601.fifo_ctl = (word)fifo_threshold;        

    init_601.hstart = hstart;
    init_601.vstart = vstart;
    init_601.hend = hend;
    init_601.vend = vend;
    init_601.compratio = dsp_bpp;
    rtnvar = rite_wavelet_chip(&init_601,0,ALL601REGS ); /* Rite ALL regs */

	// "601rpman.vxd" needs a copy of the mode control register image during 
	// the software which is required right before capture and playback !
	*ptr2ptrs->pR3_601md_ctl = init_601.mode_ctl;
	
    init_601.mode_ctl &= ~RESET_601;    /* Clear Reset to put chip on line */
    rtnvar = rite_wavelet_chip(&init_601,ADV601_WR_MdCtl,1 );  /* Write just mode_ctl reg */


	if (bwc_array != NULL && ptr2ptrs->pBWCoeffBuf != NULL )
	{
/*
Initialize the Bin Width Coefficients registers and pBWCoeffBuf[] buffer 
to a particular set of Bin Width Coefficient passed down from the caller.
This buffer is used by the run time Bin Width Calculator to pass calculated 
coefficient to the "601rpman" VxD, and when the next Statitic ready interrupt 
occurs, "601rpman" VxD will update ADV601 B.W. register from this buffer.
*/

    	for (i=0; i<84; i++)            /* how za about a memcpy here ? */ 
			ptr2ptrs->pBWCoeffBuf[i] = bwc_array[i];
		rtnvar |= rite_wavelet_chip(bwc_array, ADV601_WR_RBW0, 84);
	}


#if LATER
    test_reg = 0;                       /* Clear test register */
    rtnvar = rite_wavelet_chip(&test_reg,ADV601_WR_TestReg,1 );
#endif
    return rtnvar;  

}




DLLEXPORT int read_wavelet_chip(void * hisptr, int subaddr,int nreg )
/******************************************************************
Processing:     Do an PCI bus read into the register struct *ptr.
                A subset may be sent by setting subaddr to the desired byte
                to start at and indicating the number of bytes to read
Inputs:         ptr is address of register structure to write into.
                subaddr is the register to start with.  0 = 1st reg
                nreg is the number of data bytes to read after chip
                addr & sub address.
Outputs:        return success for now.  Future versions may detect errors.
Side-effects    None.
*******************************************************************/
{


    int rtnvar = SUCCESS;               /* Maybe something can go wrong? */
    int i;
    word *ptr;
    dword   scratch;

    ptr = (word*) hisptr;               /* defeat strong typing */

    *ptr2addr = subaddr;                // setup the starting sub-address
    for (i = 0; i < nreg; i++)          // read in data by auto-increment
    {
        scratch = *ptr2data;            /* do a 32bit PCI bus read */
        *ptr++= (word) scratch;         /* only low word counts */
    }
    return rtnvar;

}


DLLEXPORT int rite_wavelet_chip(void * hisptr, int subaddr,int nreg )
/******************************************************************
Processing:     Copy one or more words from ram into the ADV601
                A subset may be sent by setting subaddr to the desired word
                to start at and indicating the number of words to send.
                The ADV601 register address port auto increments after each
                write to the register data port, and this routine takes
                advantage of the feature when doing multiple registers.

Inputs:         ptr is address of register structure to transmit
                subaddr is the register to start with.  0 = 1st reg
                nreg is the number of data words to send after chip addr
                & sub address.
Outputs:        return success for now. Future versions may detect errors.
Side-effects    None
*******************************************************************/
{


    int rtnvar = SUCCESS;               /* Maybe something can go wrong? */
    word    *ptr;                       /* read ptr */
    int i;                              /* loop ctr */
    dword   scratch;
    
    ptr = (word*) hisptr;               /* defeat strong typing     */

    *ptr2addr = subaddr;                /* set adv601 indirect add reg */
    for (i = 0 ; i < nreg; i++)
    {
        scratch = (word) *ptr++;        /* convert 16 bits to 32 bits */
        *ptr2data= scratch;             /* do 32 bit writes using auto inc */
    }
    return rtnvar;

}


DLLEXPORT int bw_calculator_input(BWCinput *  pBWCin, dword * VxD_StatsBuf)
/******************************************************************
Processing: 
		Input the Statistic Data from the VxD buffer into the Bin
		Width Calculator.    
              
Inputs:         
                
Outputs:        
Side-effects    None.
*******************************************************************/
{
    int     rtnvar = SUCCESS;           
    int     i;

    // read in data by auto-increment
    for (i = 0; i < 42; i++)
    {
        // Make sure we do a 32bit PCI bus read 
        pBWCin->SumOfSq[i] = (word)(VxD_StatsBuf[i] & 0x0000FFFF);       
    }

    return rtnvar;

}


DLLEXPORT int bw_calculator_output(BWCoutput *  pBWCout, dword * VxD_BWCoeffBuf)
/******************************************************************
Processing:     

Inputs:         
                
Outputs:        return success 
Side-effects    None
*******************************************************************/
{

    int     rtnvar = SUCCESS;           
    int     i, j;


#if 1
    for (i = 0 ; i <= 41; i++)
    {
		j = i*2;
        VxD_BWCoeffBuf[j] = (dword)pBWCout->RBWCoeff[i];              
    	VxD_BWCoeffBuf[j+1] = (dword)pBWCout->BWCoeff[i];              
    }
#else
    for (i = 0 ; i < 84; i++)
         VxD_BWCoeffBuf[i] = (dword)med_bw[i];
#endif

    return rtnvar;
}



#define AMCC_FIFOSIZ 8

DLLEXPORT int   dma_init(dword * bufptr, int bufsiz
                         ,int direction ,EV601 * ptr2ptrs)
/******************************************************************
Processing:     Initialize AMCC bus interface DMA (bus master) mode.

Inputs:         bufsiz is in bytes (4 bytes per longword)
                direction is S_Capture or S-Playback
Outputs:        return success 
Side-effects    Profound. You won't be able to access the 601 chip
                registers until a clr_mcsrbit (DMA_ENABLE) is done. 
*******************************************************************/
{

    int rtnvar;
    AMCC_OP_REGS * ptr;
    dword mcsrdata;
    dword statword;
    int i;
    dword *src;
    int ndma;                           /* bytes to DMA */
    dword * fixedptr;                   /* fixed up ptr to physical data */

    ptr= ptr2ptrs->logicBAR0; 
    src = ptr2ptrs->bufa_logical;

    ndma = bufsiz;
    fixedptr = bufptr ;

    
    init_601.fifo_ctl = 0x0F1;        /* Do fifo_srq as soon as possible */
    rtnvar = rite_wavelet_chip(&init_601,ADV601_WR_FIFOCtl,1 );
    mcsrdata = ptr->MCSR;
    mcsrdata &= ~ (EN_A2P_XFERS | EN_P2A_XFERS
                  | A2P_HI_PRIORITY | P2A_HI_PRIORITY);
    mcsrdata |= RESET_A2P_FLAGS | RESET_P2A_FLAGS
             | A2P_BURST | P2A_BURST;
    ptr->MCSR = mcsrdata;                /* shut down DMA */
    mcsrdata &= ~(RESET_A2P_FLAGS | RESET_P2A_FLAGS);
 
    
    ptr->MWAR = fixedptr;                 /* Write address register*/
    ptr->MRAR = fixedptr;                 /* and read too */
    ptr->MWTC = ndma;                   /* write transfer count  */
    ptr->MRTC = ndma;                 /* and read too */
    if (direction == S_Capture)
    {
        mcsrdata |= A2P_HI_PRIORITY | EN_A2P_XFERS;
        ptr->MCSR = mcsrdata;
        set_mcsrbit(DMA_ENABLE);            /* Dma on, 601 registers gone */

        for ( i = 0; i < 100000 ; i++)
        {
            statword = ptr->MCSR;
            if ((statword & A2P_FIFO_EMPTY) == 0)
                break;
        }
    }
    else
    {
        mcsrdata |= P2A_HI_PRIORITY | EN_P2A_XFERS;
        ptr->MCSR = mcsrdata;
        set_mcsrbit(DMA_ENABLE);            /* Dma on, 601 registers gone */
    }
    return rtnvar;
}


/******************************************************************
Processing:		Read in the FIFO threshold value from a text file.      
				This function is only used for the purpose of H.W. 
				trouble shooting !

Inputs:         File name of a FIFO Configuration file in the 
				VideoLab directory.

Outputs:        return success or failure 

Side-effects    If the FIFO threshold text does not exist, this 
				function will return error and nothing will change.

*******************************************************************/
DLLEXPORT int read_fifo_thre_file(char *fname, byte * thre)
{
	FILE 	*fp;
	byte	thre_read;
	

	if ( (fp = fopen(fname,"r")) == NULL)
		return FAILURE;

	if (fscanf(fp, "%x", &thre_read) != 1)
	{
		fclose(fp);
		return FAILURE;
	}
	
	*thre = thre_read;
	fclose(fp);

	return SUCCESS;
}