📄 adv601.c
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/*------------------------------------------------------------------------
$Workfile: ADV601.C $
$Date: 6/20/97 3:46p $
$Revision: 27 $
* Purpose:
* ADV601 Wavelet Compression Chip support routines
* Notes:
* mcsr register is a "write only" register and a read only
* register with the same address. Do not do read-modify-write
* operations on the mcsr register. To set a single bit, call the
* set_mcsrbit and clr_mcsrbit routines.
*
$History: ADV601.C $
*
* ***************** Version 27 *****************
* User: Stevel Date: 6/20/97 Time: 3:46p
* Updated in $/601cman
* Add new header vlab.h
*
* ***************** Version 26 *****************
* User: Stevel Date: 1/07/97 Time: 6:33p
* Updated in $/601cman
* Add a new function to read in FIFO threshold from a text file for H.W.
* trouble shooting purpose !
*
* ***************** Version 25 *****************
* User: Dstarr Date: 10/25/96 Time: 1:48p
* Updated in $/601cman
* Put bits per pixel into the compression ratio register for the DSP.
*
* ***************** Version 24 *****************
* User: Dstarr Date: 10/08/96 Time: 9:53a
* Updated in $/601cman
* Support DSP bin width calc bit in the ADV601 mode control register.
*
* ***************** Version 23 *****************
* User: Dstarr Date: 8/07/96 Time: 1:26p
* Updated in $/601cman
* Support Phillips mode
*
* ***************** Version 22 *****************
* User: Stevel Date: 7/24/96 Time: 8:45p
* Updated in $/601cman
* Minor code change in wavelet_init() to help fixing the problem of
* capturing in PAL mode.
*
* ***************** Version 21 *****************
* User: Dstarr Date: 7/01/96 Time: 9:23a
* Updated in $/601cman
* Support Cropping registers.
*
* ***************** Version 20 *****************
* User: Stevel Date: 6/23/96 Time: 9:25p
* Updated in $/601cman
* Add changes to support run time Bin Width Calculation.
*
* ***************** Version 19 *****************
* User: Stevel Date: 6/06/96 Time: 1:46p
* Updated in $/601cman
* Add a new parameter for programming ADV601 FIFO threshold.
*
* ***************** Version 18 *****************
* User: Dstarr Date: 6/06/96 Time: 9:41a
* Updated in $/601cman
* dma_init() no longer stuffs fifo by hand before going to bus master
* mode.
*
* ***************** Version 17 *****************
* User: Dstarr Date: 5/29/96 Time: 8:32a
* Updated in $/601cman
* Add new function dma_init for bus master support. Clean up a few
* comments. This dma_init coudl actually move 74 long words into the
* ADV601 fifo by DMA and get them back. DMA stopped after 74 long words
* cause FIFO_SRQ went away for reasons unknown at this time.
*
*
* ***************** Version 16 *****************
* User: Stevel Date: 5/17/96 Time: 5:05p
* Updated in $/601cman
* Demo version.
*
* ***************** Version 15 *****************
* User: Stevel Date: 5/04/96 Time: 7:49p
* Updated in $/601cman
* Change the FIFO threshold back to half full !
*
* ***************** Version 14 *****************
* User: Stevel Date: 5/04/96 Time: 11:26a
* Updated in $/601cman
* Change the Encode FIFO Threshold to 3/4 FULL.
*
* ***************** Version 13 *****************
* User: Stevel Date: 4/20/96 Time: 11:26a
* Updated in $/601cman
* Minor changes in wavelet_init().
*
* ***************** Version 12 *****************
* User: Stevel Date: 4/15/96 Time: 7:48p
* Updated in $/601cman
* Change wavelet_init() to initialize ADV601 in master and unicolor mode.
*
* ***************** Version 11 *****************
* User: Dstarr Date: 4/13/96 Time: 12:17p
* Updated in $/601cman
* Wavelet Init now sets FIFO trip points to half way up the FIFO (256)
* words. When FIFO service request is asserted, you can write 256
* longwords into the FIFO.
*
* ***************** Version 10 *****************
* User: Stevel Date: 4/10/96 Time: 3:41p
* Updated in $/601cman
* Add Stop() in wavelet_init() to disable interrupt before init. ADV601.
*
* ***************** Version 9 *****************
* User: Stevel Date: 4/09/96 Time: 7:35p
* Updated in $/601cman
* Change the Interrupt polarity to active high in wavelet_init().
*
* ***************** Version 8 *****************
* User: Dstarr Date: 4/09/96 Time: 9:26a
* Updated in $/601cman
* This version does NOT do anything with the test register at 180 hex.
* Attempts to zero same seemed (haven't tested enough to be SURE) to
* cause host computer lockup.
*
* ***************** Version 7 *****************
* User: Dstarr Date: 4/05/96 Time: 4:17p
* Updated in $/601cman
* Fixed sense of encode/decode in wavelet init. S_Capture now puts the
* chip into ENCODE mode. All else is DECODE. Previous versions had this
* backwards.
*
*
* ***************** Version 6 *****************
* User: Dstarr Date: 4/05/96 Time: 11:31a
* Updated in $/601cman
* Improved wavelet init. Runs in lab.
*
* ***************** Version 5 *****************
* User: Dstarr Date: 4/03/96 Time: 11:54a
* Updated in $/601cman
* Fix bug in rite_wave_chip. We now see good data driven out the data
* bus on a rite cycle with the logic analyser.
*
* ***************** Version 4 *****************
* User: Dstarr Date: 3/13/96 Time: 5:06p
* Updated in $/601cman
* Checked out in lab. 601test can play beauty thru the DLL.
*
* ***************** Version 3 *****************
* User: Stevel Date: 3/11/96 Time: 7:32p
* Updated in $/601cman
* Rename bw_calulator_input() to bw_calculator_input().
* Change both bw_calculator_input and bw_calculator_output() not
* to perform byte swap when accessing ADV601.
*
* ***************** Version 1 *****************
* User: Stevel Date: 3/06/96 Time: 8:08p
* Created in $/601cman
* Initial release
This code and information is provided "as is" without warranty of any
kind, either expressed or implied, including but not limited to the
implied warranties of merchantability and/or fitness for a particular
purpose.
1995 Analog Devices, Inc.
-------------------------------------------------------------------------*/
#include <windows.h>
#include <stdio.h>
#include "globsym.h"
#include "amcc.h"
#include "vxdmsg.h"
#include "bw.h"
#include "adv601.h"
#include "601error.h"
#include "capplybk.h"
#include "601cman.h"
#include "vlab.h"
#include "i2c.h"
#pragma warning(disable : 4273) /* Suppress dll export assumed warning.
We are a dll, we always export and
never import */
extern int hstart;
extern int hend;
extern int vstart;
extern int vend;
extern int dsp_bpp; /* bits per pixel for the dsp */
extern word med_bw[84];
ADV601_REG init_601;
/* pointers to Eval card hardware
Note:
*/
static dword * ptr2addr; // ADV601 SubAddress Reg. address
static dword * ptr2data; // ADV601 Data Reg. address
static dword * ptr2mcsr; // ADV601 Interrupt mask and status Reg.
////////////////////////////////////////////////////////////////////////////
// In line function to perform byte swap
////////////////////////////////////////////////////////////////////////////
_inline word byte_swap(word WordIn)
{
byte LoByte, HiByte;
LoByte = (byte)WordIn;
HiByte = (byte)(WordIn >> 8);
return (LoByte << 8)| HiByte;
};
DLLEXPORT int wavelet_init( int videoformat,
int direction,
byte fifo_threshold ,
EV601 * ptr2ptrs,
word * bwc_array)
/******************************************************************
Processing: Initialize ptrs and write all 601 registers. Reset bit
should be asserted while programming ADV601 control registers
and removed while all is ready to run. It is best to first
assert reset WITHOUT the encode bit. In encode, ADV601 logic
waits for end of frame, to avoid torn frames at the end of
a video clip going to disk. This may result in reset not
taking effect for one whole frame time (30 msec).
Decode mode does NOT wait for end of frame, it resets
immediately.
Inputs: videoformat contains bits PAL, DSP_BWC, and PHILLIPS
PHILLIPS and DSP_BWC are hardware test bits usually off.
direction is true (playback) or false (record)
Outputs: return success
Side-effects None.
*******************************************************************/
{
int rtnvar, i;
#if LATER
word test_reg;
#endif
// Setup the ADV601 register address pointer
ptr2addr = ptr2ptrs->logicBAR1;
ptr2data = ptr2ptrs->logicBAR2;
ptr2mcsr = ptr2ptrs->logicBAR4;
// Stop interrupt if it happens
Stop();
memset (&init_601,0,sizeof(init_601)); /* Turn all bits OFF */
init_601.mode_ctl = RESET_601; /* Reset AND DECODE MODE */
rtnvar = rite_wavelet_chip(&init_601,0,1 ); /* Reset sluggish in ENCODE*/
init_601.mode_ctl = RESET_601 | HIRQ_ACT_HI_601 | UNI_COLOR_601 ;
// Stay in reset while
if (videoformat & PAL) /* programming all ctl regs */
init_601.mode_ctl |= PAL_601;
if (videoformat & DSP_BWC) /* if DSP does BWC */
init_601.mode_ctl |= DSP_601; /* then enable serial port */
if (videoformat & PHILLIPS) /* Special hardware test feature */
{
init_601.mode_ctl |= PLAIN_PHILLIPS ;
if (direction == S_Capture)
init_601.mode_ctl |= PHSYNC;
else
init_601.mode_ctl |= MASTER_601;
}
else /* Usual case */
init_601.mode_ctl |= CCIR_656 | MASTER_601;
if (direction == S_Capture)
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