📄 amcc.h
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/*------------------------------------------------------------------------
$Workfile: AMCC.H $
$Date: 6/20/97 2:21p $
$Revision: 11 $
* Purpose:
* Header for AMCC S5933 PCI Chip.
* Notes:
*
$History: AMCC.H $
*
* ***************** Version 11 *****************
* User: Stevel Date: 6/20/97 Time: 2:21p
* Updated in $/601cman
* Add a new variable for 601test to get error code from VxD.
*
* ***************** Version 10 *****************
* User: Stevel Date: 12/03/96 Time: 1:23p
* Updated in $/601rpman/ihbmbwc
* Add a new field in EV601 structure.
*
* ***************** Version 9 *****************
* User: Stevel Date: 7/24/96 Time: 8:12p
* Updated in $/601rpman/ihbmbwc
* Add a new field in EV601 structure for the purpose of passing the
* ADV601 Mode Control Regs in ring 3 to ring 0.
*
* ***************** Version 8 *****************
* User: Stevel Date: 6/23/96 Time: 9:26p
* Updated in $/601cman
* Add changes to support run time Bin Width Calculation.
*
* ***************** Version 7 *****************
* User: Dstarr Date: 5/24/96 Time: 10:53a
* Updated in $/601test
* fix a couple of broken bit definitions
*
* ***************** Version 6 *****************
* User: Stevel Date: 5/23/96 Time: 2:56p
* Updated in $/601rpman
* Add new bit definition for AMCC INTCSR and MCSR regisers
*
* ***************** Version 5 *****************
* User: Dstarr Date: 5/23/96 Time: 1:22p
* Updated in $/601cman
* Fix one definition
*
* ***************** Version 4 *****************
* User: Dstarr Date: 5/23/96 Time: 11:24a
* Updated in $/601cman
* Add #defines for bits in the AMCC Main Control & Status register.
* Change declaration of AMCC Read and Write address registers to dword *
* so you can put a point into them without a compiler warning. Add bufa
* and b logical and physical address words to the EV601 structure.
* 601RPman is expected to fill these in during the load_vxd call.
*
*
* ***************** Version 3 *****************
* User: Dstarr Date: 5/17/96 Time: 3:06p
* Updated in $/601test
* Add done flag declaration
*
* ***************** Version 2 *****************
* User: Stevel Date: 4/14/96 Time: 5:26p
* Updated in $/601cman
* Add PnpIRQ field in EV601 structure.
*
* ***************** Version 1 *****************
* User: Stevel Date: 3/06/96 Time: 7:53p
* Created in $/601cman
* Initial release
This code and information is provided "as is" without warranty of any
kind, either expressed or implied, including but not limited to the
implied warranties of merchantability and/or fitness for a particular
purpose.
1996 Analog Devices, Inc.
-------------------------------------------------------------------------*/
/****************************************************************************/
/* */
/* Module: AMCC.H */
/* */
/* Purpose: */
/* */
/****************************************************************************/
#ifndef AMCC
#define AMCC
#include "globsym.h"
//============================================================================
// PCI Functions
//============================================================================
#define PCI_FUNCTION_ID 0xb1
#define PCI_BIOS_PRESENT 0x01
#define FIND_PCI_DEVICE 0x02
#define FIND_PCI_CLASS_CODE 0x03
#define GENERATE_SPECIAL_CYCLE 0x06
#define READ_CONFIG_BYTE 0x08
#define READ_CONFIG_WORD 0x09
#define READ_CONFIG_DWORD 0x0a
#define WRITE_CONFIG_BYTE 0x0b
#define WRITE_CONFIG_WORD 0x0c
#define WRITE_CONFIG_DWORD 0x0d
//============================================================================
// PCI Return Code List
//============================================================================
#define SUCCESSFUL 0x00
#define NOT_SUCCESSFUL 0x01
#define FUNC_NOT_SUPPORTED 0x81
#define BAD_VENDOR_ID 0x83
#define DEVICE_NOT_FOUND 0x86
#define BAD_REGISTER_NUMBER 0x87
//============================================================================
// PCI Configuration Space Registers
//============================================================================
#define PCI_CS_VENDOR_ID 0x00
#define PCI_CS_DEVICE_ID 0x02
#define PCI_CS_COMMAND 0x04
#define PCI_CS_STATUS 0x06
#define PCI_CS_REVISION_ID 0x08
#define PCI_CS_CLASS_CODE 0x09
#define PCI_CS_CACHE_LINE_SIZE 0x0c
#define PCI_CS_MASTER_LATENCY 0x0d
#define PCI_CS_HEADER_TYPE 0x0e
#define PCI_CS_BIST 0x0f
#define PCI_CS_BASE_ADDRESS_0 0x10
#define PCI_CS_BASE_ADDRESS_1 0x14
#define PCI_CS_BASE_ADDRESS_2 0x18
#define PCI_CS_BASE_ADDRESS_3 0x1c
#define PCI_CS_BASE_ADDRESS_4 0x20
#define PCI_CS_BASE_ADDRESS_5 0x24
#define PCI_CS_RESERVED1 0x28
#define PCI_CS_RESERVED2 0x2C
#define PCI_CS_EXPANSION_ROM 0x30
#define PCI_CS_RESERVED3 0x34
#define PCI_CS_RESERVED4 0x38
#define PCI_CS_INTERRUPT_LINE 0x3c
#define PCI_CS_INTERRUPT_PIN 0x3d
#define PCI_CS_MIN_GNT 0x3e
#define PCI_CS_MAX_LAT 0x3f
//============================================================================
// AMCC Operation Register Offsets
//============================================================================
#define AMCC_OP_REG_OMB1 0x00
#define AMCC_OP_REG_OMB2 0x04
#define AMCC_OP_REG_OMB3 0x08
#define AMCC_OP_REG_OMB4 0x0c
#define AMCC_OP_REG_IMB1 0x11
#define AMCC_OP_REG_IMB2 0x14
#define AMCC_OP_REG_IMB3 0x18
#define AMCC_OP_REG_IMB4 0x1c
#define AMCC_OP_REG_FIFO 0x20
#define AMCC_OP_REG_MWAR 0x24
#define AMCC_OP_REG_MWTC 0x28
#define AMCC_OP_REG_MRAR 0x2c
#define AMCC_OP_REG_MRTC 0x30
#define AMCC_OP_REG_MBEF 0x34
#define AMCC_OP_REG_INTCSR 0x38
#define AMCC_OP_REG_MCSR 0x3c
#define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2) // Data in byte 2
#define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3) // Command in byte 3
//============================================================================
// ISA ADD-ON interface Base Address
//============================================================================
#define ISA_ADDON_ADDR 0x300
//============================================================================
// ISA Add-on interface operation registers offset
//============================================================================
#define ISA_ADDON_IMB1 0x00
#define ISA_ADDON_IMB2 0x04
#define ISA_ADDON_IMB3 0x08
#define ISA_ADDON_IMB4 0x0c
#define ISA_ADDON_OMB1 0x10
#define ISA_ADDON_OMB2 0x14
#define ISA_ADDON_OMB3 0x18
#define ISA_ADDON_OMB4 0x1c
#define ISA_ADDON_FIFO 0x20
#define ISA_ADDON_MWAR 0x24
#define ISA_ADDON_PTA 0x28
#define ISA_ADDON_PTD 0x2c
#define ISA_ADDON_MRAR 0x30
#define ISA_ADDON_MBEF 0x34
#define ISA_ADDON_INT 0x38
#define ISA_ADDON_GCSTS 0x3c
//============================================================================
// MailBox Interrupt Mask and constant
//============================================================================
#define IMB_INT_EN 0x00001000
#define IMB4_INT_SEL 0x00000C00
#define IMB4_INT_BYTE_SEL 0x00000300
#define IBM_INT_CLR 0x00020000
//============================================================================
// PCI Configuration Table structre
//============================================================================
typedef struct PCI_CFG_SP_HDR
{
word VendorID;
word DeviceID;
word Command;
word Status;
byte RevisionID;
byte ProgIfCode;
byte SubClassCode;
byte BaseClassCode;
byte CacheLineSize;
byte LatencyTimer;
byte HeaderType;
byte BIST;
dword BaseAddrReg0;
dword BaseAddrReg1;
dword BaseAddrReg2;
dword BaseAddrReg3;
dword BaseAddrReg4;
dword BaseAddrReg5;
dword Reserved1;
dword Reserved2;
dword ExpROMBaseAddr;
dword Reserved3;
dword Reserved4;
byte InterruptLine;
byte InterruptPin;
byte Min_Gnt;
byte Max_Lat;
} PCI_CFG_SP_HDR;
//============================================================================
// PCI BIOS INFO structre
//============================================================================
typedef struct PCI_INFO
{
byte bus;
byte device_function;
byte hw_mech;
byte last_bus_num;
word if_ver;
byte bus_number;
byte device_and_function;
byte pci_present_flg;
byte vendor_found_flg;
byte IRQ;
byte interrupt_vector;
} PCI_INFO;
//============================================================================
// AMCC Operation Register Base Address Structure
//============================================================================
typedef struct AMCC_OP_REGS_BASE_ADDR
{
dword addr0;
dword addr1;
dword addr2;
dword addr3;
dword addr4;
// Not use !
dword addr5;
} AMCC_OP_REGS_BASE_ADDR;
//============================================================================
// AMCC Operation Register Structure
//============================================================================
typedef struct AMCC_OP_REGS
{
dword OMB1;
dword OMB2;
dword OMB3;
dword OMB4;
dword IMB1;
dword IMB2;
dword IMB3;
dword IMB4;
dword FIFO;
dword * MWAR;
dword MWTC;
dword * MRAR;
dword MRTC;
dword MBEF;
dword INTCSR;
dword MCSR;
//dword MCSR_NVDATA;
//dword MCSR_NVCMD;
} AMCC_OP_REGS;
//============================================================================
// AMCC Interrupt Control Status Register (INTCSR) control bits
//============================================================================
#define EN_READ_TC_INT 0x00008000L
#define EN_WRITE_TC_INT 0x00004000L
// Identify AMCC interrupt sources
#define ANY_AMCC_INT 0x00800000L
#define TARGET_ABORT_INT 0x00200000L
#define MASTER_ABORT_INT 0x00100000L
#define READ_TC_INT 0x00080000L
#define WRITE_TC_INT 0x00040000L
/*
AMCC Bus master Control & Status Register (MCSR) control bits
*/
#define READ_TRAN_ENA (1L<<14)
#define READ_TRAN_ENA4 (3L<<13)
#define READ_TRAN_CMP 0x00080000L
#define MAILBOX_RESET 0x08000000L
#define RESET_A2P_FLAGS 0x04000000L
#define RESET_P2A_FLAGS 0x02000000L
#define ADD_ON_RESET 0x01000000L
#define EN_P2A_XFERS 0x00004000L /* PCI to addon DMA */
#define P2A_BURST 0x00002000L
#define P2A_HI_PRIORITY 0x00001000L
#define EN_A2P_XFERS 0x00000400L /* addon to PCI DMA */
#define A2P_BURST 0x00000200L
#define A2P_HI_PRIORITY 0x00000100L
#define A2P_TC_ISZERO 0x00000080L /* Addon to PCI is done */
#define P2A_TC_ISZERO 0x00000040L /* PCI to addon is done */
#define A2P_FIFO_EMPTY 0x00000020L
#define P2A_FIFO_EMPTY 0x00000004L
//////////////////////////////////////////////////////////////////////////////
// ISA Add-on interface operation Register Structure
//////////////////////////////////////////////////////////////////////////////
typedef struct ISA_ADDON_OP_REGS
{
dword OMB1;
dword OMB2;
dword OMB3;
dword OMB4;
dword IMB1;
dword IMB2;
dword IMB3;
dword IMB4;
dword FIFO;
dword MWAR;
dword PTA;
dword PTD;
dword MRAR;
dword MRTC;
dword MBEF;
dword INT;
dword GCSTS;
} ISA_ADDON_OP_REGS, * PISA_ADDON_OP_REGS;
//============================================================================
// ADV601 evaluation board low level driver info
//============================================================================
typedef struct EV601
{
PCI_CFG_SP_HDR * pPciCfgHdr;
AMCC_OP_REGS * logicBAR0;
dword * logicBAR1;
dword * logicBAR2;
dword * logicBAR3;
dword * logicBAR4;
dword PnpIRQ;
dword IntStatus;
dword * bufa_physical;
dword * bufa_logical;
dword * bufb_physical;
dword * bufb_logical;
dword bufsiz;
dword * pStatsBuf; // Pointer to the statistic buffer, which
// is shared by both "601rpman" VxD and
// "601cman" DLL.
dword * pBWCoeffBuf; // Pointer to the Bin Width Coeff. buffer,
// which is shared by both "601rpman" VxD
// and "601cman" DLL.
dword * pR3_601md_ctl; // point to a local copy of the ADV601 mode
// mode control register in "601cman.dll"
// we need the image of this register for
// ADV601 software reset during captue and
// playback.
dword CurFieldSz;
dword VlabErr; // another share variable pass along error
// code for 601test.
} EV601;
#endif // End of AMCC header
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