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📄 disksim_controller.c

📁 目前最精确的磁盘模拟器的第3版
💻 C
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               controller_53c700_event_arrive(currctlr, curr);               break;            case CTLR_SMART:               controller_smart_event_arrive(currctlr, curr);               break;      default:               fprintf(stderr, "Unknown controller type in controller_interrupt_arrive: %d\n", currctlr->type);               exit(1);   }}int disksim_ctlr_stats_loadparams(struct lp_block *b) {  ctlrinfo_t *ctlrinfo;  if(disksim->ctlrinfo == NULL) {    disksim->ctlrinfo = malloc(sizeof(ctlrinfo_t));    if(!disksim->ctlrinfo) return 0;    bzero((char *)disksim->ctlrinfo, sizeof(ctlrinfo_t));  }  ctlrinfo = disksim->ctlrinfo;  #include "modules/disksim_ctlr_stats_param.c"  return 1;}controller *controller_copy(controller *orig) {  controller *result = malloc(sizeof(controller));  if(!result) return 0;  memcpy(result, orig, sizeof(controller));  result->cache = cache_copy(orig->cache);  result->queue = ioqueue_copy(orig->queue);  /* don't copy these */  result->connections = 0;  result->datatransfers = 0;  result->hostwaiters = 0;  result->buswait = 0;  result->outbuses = 0;  return result;}struct controller *disksim_ctlr_loadparams(struct lp_block *b){  int c;  controller *result;  /* temp vars for parameters */    /* initialize top-level controller info struct if necessary */  if (disksim->ctlrinfo == NULL) {    disksim->ctlrinfo = DISKSIM_malloc (sizeof(ctlrinfo_t));    bzero ((char *)disksim->ctlrinfo, sizeof(ctlrinfo_t));  }    /* find a free slot in the controller table for the controller   * we're creating */  for(c = 0; c < disksim->ctlrinfo->ctlrs_len; c++) {    if(!disksim->ctlrinfo->controllers[c]) { goto foundslot; }   }  /* didn't find a free slot -- resize the controller ptr array */  {    int newlen = c ? 2*c : 2;    int zerooff = (newlen == 2) ? 0 : c;    int zerolen = ((newlen == 2) ? 2 : (newlen / 2)) * sizeof(int *);        disksim->ctlrinfo->controllers = realloc(disksim->ctlrinfo->controllers,					     newlen * sizeof(int *));        bzero(disksim->ctlrinfo->controllers + zerooff, zerolen);    disksim->ctlrinfo->ctlrs_len = newlen;  } foundslot:    disksim->ctlrinfo->numcontrollers++;  /* allocate a new controller struct */  result = malloc(sizeof(controller));  if(!result) return 0;  bzero(result, sizeof(controller));  disksim->ctlrinfo->controllers[c] = result;  bzero(result, sizeof(controller));  result->name = strdup(b->name);      #include "modules/disksim_ctlr_param.c"  /* Overhead for propogating request to lower-level component */  result->ovrhd_disk_request = 0.5;  /* Overhead for propogating ready-to-transfer to upper-level component */  result->ovrhd_ready = 0.5;  /* Overhead for propogating ready-to-transfer to lower-level component */  result->ovrhd_disk_ready = 0.5;  /* Overhead for propogating disconnect to upper-level component */  result->ovrhd_disconnect = 0.5;  /* Overhead for propogating disconnect to lower-level component */  result->ovrhd_disk_disconnect = 0.5;  /* Overhead for propogating reconnect to upper-level component */  result->ovrhd_reconnect = 0.5;  /* Overhead for propogating reconnect to lower-level component */  result->ovrhd_disk_reconnect = 0.5;  /* Overhead for propogating complete to upper-level component */  result->ovrhd_complete = 0.5;  /* Overhead for propogating complete to lower-level component */  result->ovrhd_disk_complete = 0.5;  /* Overhead for propogating disconnect/complete-complete to     upper-level component */  result->ovrhd_reset = 0.5;    return result;}void controller_read_logorg (FILE *parfile){  assert(0);/*     ctlrinfo_t *ctlrinfo = disksim->ctlrinfo; *//*     getparam_int(parfile, "\n# of controller-level organizations", &ctlrinfo->numctlorgs, 3, 0, MAXLOGORGS); *//*     fscanf(parfile, "\n"); *//*     if (ctlrinfo->numctlorgs > 0) { *//*        fprintf (stderr, "Controller-level logical organizations are not currently supported\n"); *//*        exit (0); *//*        ctlrinfo->ctlorgs = logorg_readparams(parfile, ctlrinfo->numctlorgs, *//*               ctlrinfo->ctl_printlocalitystats, ctlrinfo->ctl_printblockingstats, *//*               ctlrinfo->ctl_printinterferestats, ctlrinfo->ctl_printstreakstats, *//*               ctlrinfo->ctl_printstampstats, ctlrinfo->ctl_printintarrstats, *//*               ctlrinfo->ctl_printidlestats, ctlrinfo->ctl_printsizestats); *//*     } */}int controller_set_depth (int ctlno, int inbusno, int depth, int slotno){   controller *currctlr = getctlr (ctlno);   intchar ret;   int i;   int cnt;/*fprintf (outputfile, "controller_set_depth %d, inbusno %d, depth %d, slotno %d\n", ctlno, inbusno, depth, slotno);*/   cnt = currctlr->numinbuses;   if ((cnt > 0) && (currctlr->depth[(cnt-1)] < depth)) {      return(0);   }   currctlr->numinbuses++;   if ((cnt + 1) > MAXINBUSES) {      fprintf(stderr, "Too many inbuses specified for controller %d : %d\n", ctlno, (cnt+1));      exit(1);   }   currctlr->inbuses[cnt] = inbusno;   currctlr->depth[cnt] = depth;   currctlr->slotno[cnt] = slotno;   ret.value = 0;   for (i = 0; i < currctlr->numoutbuses; i++) {      ret.byte[i] = (char) currctlr->outbuses[i];      currctlr->outslot[i] = bus_get_controller_slot(ret.byte[i], ctlno);   }   return(ret.value);}int controller_get_bus_master (int busno){   ctlrinfo_t *ctlrinfo = disksim->ctlrinfo;   int i;   int j;   for (i = 0; i < ctlrinfo->numcontrollers; i++) {      controller *currctlr = getctlr(i);      for (j = 0; j < currctlr->numoutbuses; j++) {         if (currctlr->outbuses[j] == busno) {            return(i);         }      }   }   return(-1);}int controller_get_outslot (int ctlno, int busno){   int i;   int slotno = 0;   controller *currctlr = getctlr(ctlno);   for (i = 0; i < currctlr->numoutbuses; i++) {      if (currctlr->outbuses[i] == busno) {         slotno = currctlr->outslot[i];         break;      }   }/*     ASSERT(slotno != 0); */   return(slotno);}int controller_get_numcontrollers (){   ctlrinfo_t *ctlrinfo = disksim->ctlrinfo;   return (ctlrinfo->numcontrollers);}int controller_get_depth (int ctlno){   controller *currctlr = getctlr(ctlno);   return (currctlr->depth[0]);}int controller_get_inbus (int ctlno){   controller *currctlr = getctlr(ctlno);   return (currctlr->inbuses[0]);}int controller_get_slotno (int ctlno){   controller *currctlr = getctlr(ctlno);   return (currctlr->slotno[0]);}int controller_get_maxoutstanding (int ctlno){   controller *currctlr = getctlr(ctlno);   return (currctlr->maxoutstanding);}void controller_setcallbacks (){   controller_smart_setcallbacks ();}void controller_initialize(){   ctlrinfo_t *ctlrinfo = disksim->ctlrinfo;   int i;   for (i = 0; i < ctlrinfo->numcontrollers; i++) {      controller *currctlr = getctlr(i);      currctlr->ctlno = i;      currctlr->state = FREE;      addlisttoextraq((event **) &currctlr->connections);      addlisttoextraq((event **) &currctlr->buswait);      addlisttoextraq((event **) &currctlr->datatransfers);      addlisttoextraq((event **) &currctlr->hostwaiters);      currctlr->hosttransfer = FALSE;      currctlr->inbusowned = -1;      currctlr->outbusowned = -1;      currctlr->waitingforbus = 0.0;      if (currctlr->type == CTLR_SMART) {         controller_smart_initialize(currctlr);      }   }}void controller_resetstats(){   ctlrinfo_t *ctlrinfo = disksim->ctlrinfo;   int i;   for (i=0; i<ctlrinfo->numcontrollers; i++) {      controller *currctlr = getctlr(i);      currctlr->waitingforbus = 0.0;      if (currctlr->type == CTLR_SMART) {         controller_smart_resetstats(currctlr);      }   }}void controller_printstats(){   ctlrinfo_t *ctlrinfo = disksim->ctlrinfo;   int ctlno;   char prefix[81];   double waitingforbus = 0.0;   fprintf (outputfile, "\nCONTROLLER STATISTICS\n");   fprintf (outputfile, "---------------------\n\n");   for (ctlno=0; ctlno < ctlrinfo->numcontrollers; ctlno++) {      controller *currctlr = getctlr(ctlno);      waitingforbus += currctlr->waitingforbus;      if (currctlr->printstats == 0) {         continue;      }      sprintf(prefix, "Controller #%d ", ctlno);      fprintf (outputfile, "%s\n\n", prefix);      switch(currctlr->type) {         case CTLR_PASSTHRU:            controller_passthru_printstats(currctlr, prefix);            break;         case CTLR_BASED_ON_53C700:            controller_53c700_printstats(currctlr, prefix);            break;         case CTLR_SMART:            controller_smart_printstats(currctlr, prefix);            break;         default:            fprintf(stderr, "Unknown controller type in controller_printstats: %d\n", currctlr->type);            exit(1);       }   }   fprintf (outputfile, "Total controller bus wait time: %f\n", waitingforbus);}void controller_cleanstats(){}int load_ctlr_topo(struct lp_topospec *t, int *inbus) {  int c;  controller *ctlr;  int num;  struct lp_topospec *ts;  int slots;  assert(!strcmp(t->type, disksim_mods[DISKSIM_MOD_CTLR]->name));  ctlr = getctlrbyname(t->name, &num);  if(!ctlr) {    fprintf(stderr, "*** error: no such controller %s\n", t->name);    return 0;  }  if(inbus) {    ctlr->inbuses[0] = *inbus;  }  if(!ctlr->outbuses) {    ctlr->numoutbuses = 0;    slots = t->l->values_len;    ctlr->outbuses = malloc(slots * sizeof(int));    bzero(ctlr->outbuses, slots * sizeof(int));  }  for(c = 0; c < t->l->values_len; c++) {    if(!t->l->values[c]) continue;    assert(t->l->values[c]->v.t.len == 1);    ts = &t->l->values[c]->v.t.l[0];    if(!strcmp(ts->type, disksim_mods[DISKSIM_MOD_BUS]->name)) {      getbusbyname(ts->name, &ctlr->outbuses[c]);      if(ctlr->outbuses[c] == -1) {	fprintf(stderr, "*** error: No such bus: %s\n", ts->name);	return 0;      }      if(!load_bus_topo(ts, &num)) {	fprintf(stderr, "*** error: failed to load bus topology spec for controller %s.\n", t->name);	return 0;      }      ctlr->numoutbuses++;    }    else {      fprintf(stderr, "*** error: can only attach buses to controllers %s\n", t->name);      return 0;    }  }  return 1;}

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