an68.c

CC386 is a general-purpose 32-bit C compiler. It is not an optimizing compiler but given that the co

/* 
Copyright 1994-2003 Free Software Foundation, Inc.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA.  

This program is derived from the cc68k complier by 
Matthew Brandt ([e-mail]) 

You may contact the author of this derivative at:

mailto::[e-mail]

or by snail mail at:

David Lindauer
850 Washburn Ave Apt 99
Louisville, KY 40222
 */
/*
 * 22-Aug-1999 (SJS) Modified for ColdFire movem instruction restrictions.
 * 07-May-2001 (SJS) Modified alloc/free of data/address registers.
 */
#include <stdio.h>
#include <string.h>
#include "lists.h"
#include "expr.h"
#include "c.h"
#include "gen68.h"
#include "diag.h"
#include "rtti.h"

/* pc-relative expressions not optimized */
extern int linkreg, basereg;
extern AMODE push[], pop[], mvma7[], mvma7i[];
extern OCODE *peep_tail;
extern SYM *currentfunc;
extern int prm_stackcheck, prm_phiform, prm_linkreg, prm_datarel, prm_smalldata,
    prm_68020;
extern int prm_coldfire;
extern int floatregs, dataregs, addrregs;
extern long framedepth, stackdepth;
extern int cf_maxfloat, cf_maxaddress, cf_maxdata;
extern int cf_freedata, cf_freeaddress;
extern CSE *olist; /* list of optimizable expressions */
extern int prm_smartframes;
extern int nextlabel;
extern int prm_xcept, conscount, xceptoffs;
extern TRYBLOCK *try_block_list;
extern int prm_cplusplus, prm_xcept;

int floatstack_mode;
long lc_maxauto;
int save_mask, fsave_mask;
int rmaskcnt;
OCODE *frame_ins;
void reserveregs(int *datareg, int *addreg, int *floatreg)
/*
 * Reserve regs goes through and reserves a register for variables with
 * the REGISTER keyword.  Note that it currently does register allocation
 * backwards...
 */
{
    CSE *csp = olist;

    while (csp)
    {
        switch (csp->exp->nodetype)
        {
            case en_fcomplexref:
            case en_rcomplexref:
            case en_lrcomplexref:
            case en_ll_ref:
            case en_ull_ref:
                break;
            case en_fimaginaryref:
            case en_rimaginaryref:
            case en_lrimaginaryref:
            case en_floatref:
            case en_doubleref:
            case en_longdoubleref:
            case en_b_ref:
            case en_bool_ref:
            case en_w_ref:
            case en_l_ref:
            case en_ub_ref:
            case en_uw_ref:
            case en_ul_ref:
			case en_i_ref:
			case en_ui_ref:
			case en_a_ref: case en_ua_ref:
                if (csp->exp->v.p[0]->nodetype != en_autoreg)
                    break;
                if (csp->size > 6)
                {
                    if (*floatreg < cf_maxfloat && floatregs)
                        csp->reg = (*floatreg)++;
                }
                else if (csp->size != 6 && csp->size !=  - 6)
                {
                    if ((*datareg < cf_maxdata) && (csp->duses <= csp->uses / 4)
                        && dataregs)
                        csp->reg = (*datareg)++;
                    else if (!(csp->size == 1 || csp->size ==  - 1) && (*addreg
                        < cf_maxaddress) && addrregs)
                        csp->reg = (*addreg)++;
                }
                if (csp->reg !=  - 1)
                {
                    ((SYM*)csp->exp->v.p[0]->v.p[0])->inreg = TRUE;
                    ((SYM*)csp->exp->v.p[0]->v.p[0])->value.i =  - csp->reg -
                        csp->size *256;
                }
                break;
        }
        csp = csp->next;
    }
}

//-------------------------------------------------------------------------

void allocate(int datareg, int addreg, int floatreg, SNODE *block)
/*
 *      allocate will allocate registers for the expressions that have
 *      a high enough desirability.
 */
{
    CSE *csp;
    ENODE *exptr,  *mvn1,  *mvn2;
    unsigned mask, i, fmask, size;
    AMODE *ap,  *ap2,  *ap3;
    framedepth = 4+lc_maxauto;
    rmaskcnt = 0;
    mask = 0;
    fmask = 0;
    for (i = cf_freedata; i < datareg; i++)
    {
        framedepth += 4;
        mask = mask | (1 << i);
    }
    for (i = cf_freeaddress + 16; i < addreg; i++)
    {
        framedepth += 4;
        mask = mask | (1 << (i - 8));
    }
    while (bsort(&olist))
        ;
     /* sort the expression list */
    csp = olist;
    while (csp != 0)
    {
        if (csp->reg ==  - 1 && !(csp->exp->cflags &DF_VOL) && !csp->voidf)
        {
            if (desire(csp) < 3)
                csp->reg =  - 1;
            else
            {
                if (csp->size > 4)
                {
                    if (floatreg < cf_maxfloat && floatregs)
                        csp->reg = floatreg++;
                }
                else if ((datareg < cf_maxdata) && (csp->duses <= csp->uses / 4)
                    && dataregs)
                    csp->reg = datareg++;
                else if (!(csp->size == 1 || csp->size ==  - 1) && (addreg <
                    cf_maxaddress) && addrregs)
                    csp->reg = addreg++;
            }
        }
        if (csp->reg !=  - 1)
        {
            if (lvalue(csp->exp) && !((SYM*)csp->exp->v.p[0]->v.p[0])->funcparm)
            {
                ((SYM*)csp->exp->v.p[0]->v.p[0])->inreg = TRUE;
                ((SYM*)csp->exp->v.p[0]->v.p[0])->value.i =  - csp->reg - csp
                    ->size *256;
            }
            if (csp->reg < 16)
            {
                framedepth += 4;
                mask = mask | (1 << csp->reg);
                rmaskcnt++;
            }
            else if (csp->reg < 32)
            {
                framedepth += 4;
                mask = mask | (1 << (csp->reg - 8));
                rmaskcnt++;
            }
            else
            {
                framedepth += 12;
                fmask = fmask | (1 << (csp->reg - 32));
            }
        }
        csp = csp->next;
    }
    allocstack(); /* Allocate stack space for the local vars */
    floatstack_mode = 0; /* no space for floating point temps */
    if (currentfunc->tp->lst.head != 0 && currentfunc->tp->lst.head != (SYM*) -
        1)
    {
        if (prm_phiform || currentfunc->intflag)
        {
            mask |= (1 << (linkreg + 8));
            framedepth += 4;
        }
        if (currentfunc->intflag)
        {
            mask |= 0xffff;
            framedepth = lc_maxauto;
        }
    }
    if ((conscount || try_block_list || currentfunc->value.classdata.throwlist
        && currentfunc->value.classdata.throwlist->data) && prm_xcept)
    {
        xceptoffs = lc_maxauto += sizeof(XCEPTDATA);
    }
    if (prm_cplusplus && prm_xcept || prm_linkreg && !currentfunc->intflag && 
        (currentfunc->tp->lst.head && currentfunc->tp->lst.head != (SYM*) - 1 
        || lc_maxauto) || !prm_smartframes || (currentfunc
        ->value.classdata.cppflags &PF_MEMBER) && !(currentfunc
        ->value.classdata.cppflags &PF_STATIC))
    {
        gen_codes(op_link, !prm_smalldata && !prm_68020 ? 2 : 4, makeareg
            (linkreg), make_immed( - lc_maxauto));
        frame_ins = peep_tail;
    }
    else
        frame_ins = 0;
    if (mask != 0)
    {
        if (prm_coldfire)
        {
            if (rmaskcnt > 1)
            {
                mvn2 = xalloc(sizeof(struct enode));
                mvn2->nodetype = en_icon;
                mvn2->v.i = (rmaskcnt << 2);
                mvn1 = xalloc(sizeof(struct enode));
                mvn1->nodetype = en_uminus;
                mvn1->v.p[0] = mvn2;
                ap3 = xalloc(sizeof(struct amode));
                ap3->mode = am_indx;
                ap3->preg = ap3->preg = 7;
                ap3->offset = mvn1;
                gen_codes(op_lea, 0, ap3, mvma7i);
                gen_codes(op_movem, 4, make_mask(mask, 0), mvma7);
                freeop(ap3);
            }
            else
                gen_codes(op_move, 4, make_mask(mask, 0), push);
        }
        else
            gen_codes(op_movem, 4, make_mask(mask, 0), push);
    }
    save_mask = mask;
    if (fmask != 0)
        gen_codes(op_fmovem, 10, make_mask(fmask, 1), push);
    fsave_mask = fmask;
    if ((prm_phiform || currentfunc->intflag) && currentfunc->tp->lst.head &&
        currentfunc->tp->lst.head != (SYM*) - 1)
    {
        gen_codes(op_move, 4, makeareg(0), makeareg(linkreg));
    } if ((!prm_linkreg || currentfunc->intflag) && lc_maxauto)
    {
        AMODE *ap = xalloc(sizeof(AMODE));
        ap->mode = am_indx;
        ap->offset = makeintnode(en_icon,  - lc_maxauto);
        ap->preg = 7;
        gen_codes(op_lea, 0, ap, makeareg(7));
    }

    if (prm_stackcheck)
    {
        AMODE *ap1;
        ap = set_symbol("__stackerror", 1);
        ap1 = set_symbol("__stackbottom", 0);
        if (prm_datarel)
        {
            ap1->mode = am_indx;
            ap1->preg = basereg;
        }
        else
        {
            ap1->mode = am_adirect;
            if (prm_smalldata)
                ap1->preg = 2;
            else
                ap1->preg = 4;
        }
        gen_codes(op_cmp, 4, ap1, makeareg(7));
        gen_codes(op_bhi, 0, ap, 0);
    }
    AddProfilerData();
    if ((conscount || try_block_list || currentfunc->value.classdata.throwlist
        && currentfunc->value.classdata.throwlist->data) && prm_xcept)
    {
        currentfunc->value.classdata.conslabel = nextlabel++;
        currentfunc->value.classdata.destlabel = nextlabel++;
        gen_codes(op_move, 4, make_label(nextlabel - 2), makedreg(0));
        call_library2("__InitExceptBlock", 0);
        gen_label(nextlabel - 1);
    }
}

//-------------------------------------------------------------------------

void loadregs(void)
/*
 * Initailze allocated regs
 *
 */
{
    CSE *csp;
    ENODE *exptr;
    unsigned mask, i, fmask, size;
    AMODE *ap,  *ap2;
    csp = olist;
    while (csp != 0)
    {
        int sz;
        if (csp->reg !=  - 1)
        {
             /* see if preload needed */
            exptr = csp->exp;
            if (!lvalue(exptr) || ((SYM*)exptr->v.p[0]->v.p[0])->funcparm)
            {
                exptr = csp->exp;
                initstack();
                sz = csp->size;
                ap = gen_expr(exptr, FALSE, TRUE, sz);
                if (sz == 0 && ap->mode == am_immed)
                    sz = 4;
                if (csp->reg < 16)
                {
                    if (sz == 0 && ap->mode == am_immed)
                        sz = 4;
                    /* might get both a move and an and */
                    if (ap->mode == am_dreg)
                    {
                        peep_tail->oper2->preg = csp->reg;
                        if (peep_tail->opcode != op_move)
                        {
                            OCODE *peep_pos = peep_tail->back;
                            peep_pos->oper2->preg = csp->reg;
                        }
                    }
                    else
                    {
                        ap2 = makedreg(csp->reg);
                        gen_codes(op_move, sz, ap, ap2);
                        do_extend(ap2, 4, F_DREG);
                    }
                }
                else
                if (csp->reg < 32)
                {
                    if (sz == 0 && ap->mode == am_immed)
                        sz = 4;
                    if (ap->mode == am_areg)
                        peep_tail->oper2->preg = csp->reg - 16;
                    else
                    {
                        ap2 = makeareg(csp->reg - 16);
                        gen_codes(op_move, 4, ap, ap2);
                    }
                }
                else
                {
                    if (sz == 0 && ap->mode == am_immed)
                        sz = 8;
                    if (ap->mode == am_freg)
                        peep_tail->oper2->preg = csp->reg - 32;
                    else