hal_clk.c

一个图形显示芯片s1d13505的应用程序

/*
**===========================================================================
** HAL_CLK.C
**---------------------------------------------------------------------------
** Copyright (c) 1998 Epson Research and Development, Inc.
** All Rights Reserved.
**===========================================================================
*/

#include "hal.h"
#include "assert.h"
#include "nonsefns.h"

/*-------------------------------------------------------------------------*/

static const char Revision[] = "HAL_CLK.C=$Revision: 1 $";

// Maximum EDO PClk / MClk ratios for 
// FPM_Ratio[MEM_TYPE][INK_ACTIVE][DISPLAY_TYPE][Nrc][BPP]
int ClkRatio[2][2][3][3][6] =
{
   /* EDO-DRAM */
   {
      /* Ink Layer Off */
      {
         {
            1, 1, 1, 1, 1, 1,
            1, 1, 1, 1, 1, 1,
            1, 1, 1, 1, 1, 1,
         },
         {
            2, 2, 2, 2, 3, 3,
            1, 1, 2, 2, 2, 2,
            1, 1, 1, 2, 2, 2,
         },
         {
            2, 2, 2, 2, 3, 3,
            2, 2, 2, 2, 3, 3,
            1, 2, 2, 2, 2, 2
         }
      },

      /* Ink Layer On */
      {
         {
            1, 1, 1, 2, 2, 2,
            1, 1, 1, 1, 2, 2,
            1, 1, 1, 1, 2, 2,
         },
         {
            2, 2, 2, 2, 3, 3,
            2, 2, 2, 2, 3, 3,
            1, 2, 2, 2, 2, 2,
         },
         {
            2, 2, 2, 3, 3, 3,
            2, 2, 2, 2, 3, 3,
            2, 2, 2, 2, 3, 3
         }
      },
   },

   /* FPM-DRAM */
   {
      /* Ink Layer Off */
      {
         {
            1, 1, 1, 1, 1, 1,
            1, 1, 1, 1, 1, 1,
            1, 1, 1, 1, 1, 1,
         },
         {
            2, 2, 2, 2, 2, 2,
            1, 1, 2, 2, 2, 2,
            1, 1, 1, 2, 2, 2,
         },
         {
            2, 2, 2, 2, 3, 3, 
            2, 2, 2, 2, 3, 3,
            1, 1, 2, 2, 2, 2
         }
      },

      /* Ink Layer On */
      {
         {
            1, 1, 1, 2, 2, 2,
            1, 1, 1, 1, 2, 2,
            1, 1, 1, 1, 2, 2,
         },
         {
            2, 2, 2, 2, 3, 3,
            2, 2, 2, 2, 3, 3,
            1, 1, 2, 2, 2, 2,
         },
         {
            2, 2, 2, 3, 3, 3, 
            2, 2, 2, 2, 3, 3,
            2, 2, 2, 2, 3, 3
         }
      },
   }
};

/*-------------------------------------------------------------------------*/

int CheckMaxPClkRatio(int seReserved1, int *ratio)
   {
   int MemType;
   int InkActive;
   int DisplayType;
   int Nrc;
   UINT BPP;

   BYTE regMemoryConfig;
   BYTE regPanelType;
   BYTE regDisplayMode;
   BYTE regMisc;
   BYTE regPerfEnhan0;
   BYTE regInkCursorCtrl;
   BYTE regClockConfig;

   ASSERT(seReserved1 == 0);

   regMemoryConfig = ReadRegister(seReserved1, REG_MEMORY_CONFIG);
   regPanelType = ReadRegister(seReserved1, REG_PANEL_TYPE);
   regDisplayMode = ReadRegister(seReserved1, REG_DISPLAY_MODE);
   regMisc = ReadRegister(seReserved1, REG_MISC);
   regPerfEnhan0 = ReadRegister(seReserved1, REG_PERF_ENHANCEMENT0);
   regInkCursorCtrl = ReadRegister(seReserved1, REG_INK_CURSOR_CONTROL);
   regClockConfig = ReadRegister(seReserved1, REG_CLOCK_CONFIG);


   /*
   ** Determine MemType
   */
   MemType = regMemoryConfig & 0x01;

   /*
   ** Determine InkActive
   */
   if ((regInkCursorCtrl & 0xc0) == 0x80)
      InkActive = 1;
   else
      InkActive = 0;

   /*------------------------------*/
   /*
   ** Determine DisplayType
   */
   DisplayType = 0;

   /* only panel, dual mono with half frame buffer enabled */
   if (((regDisplayMode & 0x03) == 0x01) &&  /* just panel active */
        (regPanelType & 0x02) &&             /* dual */
       !(regPanelType & 0x04) &&             /* mono */
       !(regMisc & 0x01))                    /* half frame buffer enabled */
      DisplayType = 1;

   /* simultaneous CRT + dual mono panel with half frame buffer enable */
   if (((regDisplayMode & 0x03) == 0x03) &&  /* panel and crt active */
        (regPanelType & 0x02) &&             /* dual */
       !(regPanelType & 0x04) &&             /* mono */
       !(regMisc & 0x01))                    /* half frame buffer enabled */
      DisplayType = 1;

   /* only panel, dual color with half frame buffer enabled */
   if (((regDisplayMode & 0x03) == 0x01) &&  /* just panel active */
        (regPanelType & 0x02) &&             /* dual */
        (regPanelType & 0x04) &&             /* color */
       !(regMisc & 0x01))                    /* half frame buffer enabled */
      DisplayType = 2;

   /* simultaneous CRT + dual color panel with half frame buffer enable */
   if (((regDisplayMode & 0x03) == 0x03) &&  /* panel and crt active */
        (regPanelType & 0x02) &&             /* dual */
        (regPanelType & 0x04) &&             /* color */
       !(regMisc & 0x01))                    /* half frame buffer enabled */
      DisplayType = 2;

   /*------------------------------*/

   /*
   ** Determine Nrc
   */
   Nrc = (regPerfEnhan0 >> 5) & 0x03;

   if (Nrc > 2)
      Nrc  = 0;


   /*
   ** Determine BPP (actual contents of register which represents bpp)
   */
   BPP = (regDisplayMode >> 2) & 0x07;


   *ratio = ClkRatio[MemType][InkActive][DisplayType][Nrc][BPP];

   /*
   ** Check if clock divide register is programmed too low.
   */
   if (((regClockConfig & 0x03)+1) < *ratio)
      return ERR_FAILED;
   else
      return ERR_OK;
   }

/*-------------------------------------------------------------------------*/