init.c

一个图形显示芯片s1d13505的应用程序

  /*
  ** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
  */
  *(pRegs + 0x0C) = 0x00;              /* 0000 0000 */

  /*
  ** Register D: Display Mode - 8 BPP, LCD disabled.
  */
  *(pRegs + 0x0D) = 0x0C;              /* 0000 1100 */

  /*
  ** Registers E-F: Screen 1 Line Compare - unless setting up for
  **                split screen operation use 0x3FF.
  */
  *(pRegs + 0x0E) = 0xFF;              /* 1111 1111 */
  *(pRegs + 0x0F) = 0x03;              /* 0000 0011 */

  /*
  ** Registers 10-12: Screen 1 Display Start Address - start at the
  **                  first byte in display memory.
  */
  *(pRegs + 0x10) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x11) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x12) = 0x00;              /* 0000 0000 */

  /*
  ** Register 13-15: Screen 2 Display Start Address - not applicable
  **                 unless setting up for split screen operation.
  */
  *(pRegs + 0x13) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x14) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x15) = 0x00;              /* 0000 0000 */

  /*
  ** Register 16-17: Memory Address Offset - this address represents the
  **                 starting WORD. At 8BPP our 640 pixel width is 320
  **                 WORDS
  */
  *(pRegs + 0x16) = 0x40;              /* 0100 0000 */
  *(pRegs + 0x17) = 0x01;              /* 0000 0001 */

  /*
  ** Register 18: Pixel Panning
  */
  *(pRegs + 0x18) = 0x00;              /* 0000 0000 */

  /*
  ** Register 19: Clock Configuration - In this case we must divide
  **              PCLK by 2 to arrive at the best frequency to set
  **              our desired panel frame rate.
  */
  *(pRegs + 0x19) = 0x01;              /* 0000 0001 */

  /*
  ** Register 1A: Power Save Configuration - enable LCD power, CBR refresh,
  **              not suspended.
  */
  *(pRegs + 0x1A) = 0x00;              /* 0000 0000 */

  /*
  ** Register 1C-1D: MD Configuration Readback - these registers are
  **                 read only, but it's OK to write a 0 to keep
  **                 the register configuration logic simpler.
  */
  *(pRegs + 0x1C) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x1D) = 0x00;              /* 0000 0000 */

  /*
  ** Register 1E-1F: General I/O Pins Configuration
  */
  *(pRegs + 0x1E) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x1F) = 0x00;              /* 0000 0000 */

  /*
  ** Register 20-21: General I/O Pins Control
  */
  *(pRegs + 0x20) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x21) = 0x00;              /* 0000 0000 */

  /*
  ** Registers 24-26: LUT control.
  **                  For this example do a typical 8 BPP LUT setup.
  **
  ** Setup the pointer to the LUT data and reset the LUT index register.
  ** Then, loop writing each of the RGB LUT data elements.
  */
  pLUT = LUT8;
  *(pRegs + 0x24) = 0;

  for (idx = 0; idx < 256; idx++)
  {
    for (rgb = 0; rgb < 3; rgb++)
    {
      *(pRegs + 0x26) = *pLUT;
      pLUT++;
    }
  }

  /*
  ** Register 27: Ink/Cursor Control - disable ink/cursor
  */
  *(pRegs + 0x27) = 0x00;              /* 0000 0000 */

  /*
  ** Registers 28-29: Cursor X Position
  */
  *(pRegs + 0x28) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x29) = 0x00;              /* 0000 0000 */

  /*
  ** Registers 2A-2B: Cursor Y Position
  */
  *(pRegs + 0x2A) = 0x00;              /* 0000 0000 */
  *(pRegs + 0x2B) = 0x00;              /* 0000 0000 */

  /*
  ** Registers 2C-2D: Ink/Cursor Color 0 - blue
  */
  *(pRegs + 0x2C) = 0x1F;              /* 0001 1111 */
  *(pRegs + 0x2D) = 0x00;              /* 0000 0000 */

  /*
  ** Registers 2E-2F: Ink/Cursor Color 1 - green
  */
  *(pRegs + 0x2E) = 0xE0;              /* 1110 0000 */
  *(pRegs + 0x2F) = 0x07;              /* 0000 0111 */

  /*
  ** Register 30: Ink/Cursor Start Address Select
  */
  *(pRegs + 0x30) = 0x00;              /* 0000 0000 */

  /*
  ** Register 31: Alternate FRM Register
  */
  *(pRegs + 0x31) = 0x00;


  /*
  ** Register 23: Performance Enhancement - display FIFO enabled, optimum
  **              performance. The FIFO threshold is set to 0x00; for
  **              15/16 bpp modes, set the FIFO threshold
  **              to a higher value, such as 0x1B.
  */
  *(pRegs + 0x23) = 0x00;              /* 0000 0000 */

  /*
  ** Register D: Display Mode - 8 BPP, LCD enable.
  */
  *(pRegs + 0x0D) = 0x0D;              /* 0000 1101 */



  /*
  ** Clear memory by filling 2 MB with 0
  */
  pMem = DISP_MEM_OFFSET;

  for (lpCnt = 0; lpCnt < DISP_MEMORY_SIZE; lpCnt++)
  {
    *pMem = 0;
    pMem++;
  }

  /*
  ** Draw a 100x100 red rectangle in the upper left corner (0, 0)
  ** of the display.
  */
  pMem = DISP_MEM_OFFSET;

  for (y = 0; y < 100; y++)
  {
    pTmp = pMem + y * 640L;

    for (x = 0; x < 100; x++)
    {
      *pTmp = 0x0c;
      pTmp++;
    }
  }

  /*
  ** Init the HW cursor. In this example the cursor memory will be located
  ** immediately after display memory. Why here? Because it's an easy
  ** location to calculate and will not interfere with the half frame buffer.
  ** Additionally, the HW cursor can be turned into an ink layer quite
  ** easily from this location.
  */
  *(pRegs + 0x30) = CURSOR_START;

  pTmp = pCursor = pMem + (DISP_MEMORY_SIZE - (CURSOR_START * 8192L));

  /*
  ** Set the contents of the cursor memory such that the cursor
  ** is transparent. To do so, write a 10101010b pattern in each byte.
  ** The cursor is 2 bpp so a 64x64 cursor requires
  ** 64/4 * 64 = 1024 bytes of memory.
  */
  for (lpCnt = 0; lpCnt < 1024; lpCnt++)
    {
    *pTmp = 0xAA;
    pTmp++;
    }

  /*
  ** Set the first user definable cursor color to black and
  ** the second user definable cursor color to white.
  */
  *(pRegs + 0x2C) = 0;
  *(pRegs + 0x2D) = 0;
  *(pRegs + 0x2E) = 0xFF;
  *(pRegs + 0x2F) = 0xFF;

  /*
  ** Draw a hollow rectangle around the cursor.
  */
  pTmp = pCursor;

  for (lpCnt = 0; lpCnt < 16; lpCnt++)
  {
    *pTmp = 0x55;
    pTmp++;
  }

  for (lpCnt = 0; lpCnt < 14; lpCnt++)
  {
    *pTmp = 0x6A;
    pTmp += 15;

    *pTmp = 0xA9;
    pTmp++;
  }

  for (lpCnt = 0; lpCnt < 16; lpCnt++)
  {
    *pTmp = 0x55;
    pTmp++;
  }

  /*
  ** Move the cursor to 100, 100.
  */

  /*
  ** First we wait for the next vertical non-display
  ** period before updating the position registers.
  */
  while (*(pRegs + 0x0A) & 0x80);     /* wait while in VNDP */

  while (!(*(pRegs + 0x0A) & 0x80));  /* wait while in VDP */

  /*
  ** Now update the position registers.
  */
  *(pRegs + 0x28) = 100;   /* Set Cursor X = 100 */
  *(pRegs + 0x29) = 0x00;

  *(pRegs + 0x2A) = 100;   /* Set Cursor Y = 100 */
  *(pRegs + 0x2B) = 0x00;

  /*
  ** Enable the hardware cursor.
  */
  *(pRegs + 0x27) = 0x40;
}