start.src

uc/os在c167上的移植代码

	MOV	R6, [R4+]		; specified ram data block. 
					; MSW=R6, LSW=R5 (long word)
					;
CB07_2:	CMPD1	R5, #0			; test if all bytes are cleared and
	JMP	CC_NE, CB07_1 		; decrement number of bytes to clear.
	CMPD1	R6, #0			;
  	JMP	CC_EQ, BSS		; if( block end ) next initialization
  
CB07_1:	MOVB	[SOF_RAM], ZEROS	; clear byte
	CMPI1	SOF_RAM, #07FFFH	; test end of data page and inc SOF_RAM
	JMP	CC_NE, CB07_2		; if(no page end) next byte clear
	MOV	SOF_RAM, #04000H	; preset offset address ram data
	ADD	DPP1, #1		; next page ram data; increment DPP1
	JMP	CC_UC, CB07_2		; jump for next byte clear
  

BSS_06:					; clear far ram data. (CPU mode is
					; segmented with DPP usage linear or
					; paged.)
	MOV	POF_RAM, [R4+]		; move intra-page offset address ram
					; data block to POF_RAM=R1
	BFLDH	SOF_RAM, #0C0H, #040H	; DPP1:POF_RAM ->SOF_RAM=R1
	MOV	DPP1, [R4]		; load data page pointer register DPP1
					; with data page of ram data block
	ADD	R4, #2			; inc offset address to ram data section
					; C166_BSS and also insure a delay for 
					; pipeline effect. (DPP1 set)
					;
	MOV	R5, [R4+]		; number of bytes to clear in specified
					; ram data block
					;
CB06_1:	CMPD1	R5, #0			; test on data block end
  	JMP	CC_EQ, BSS		; if( block end ) next initialization
  
	MOVB	[SOF_RAM], ZEROS	; clear byte
	ADD	SOF_RAM, #1		; inc SOF_RAM
	JMP	CC_UC, CB06_1		; jump for next byte clear
  



BSS_END:

  

      	MOV 	DPP0, #0		 ; restore DPP0 to its default value
	MOV	DPP1, #PAG ?USRSTACK_TOP ; set DPP1 to page of user stack
	MOV	DPP2, #PAG C166_DGROUP	 ; set DPP2 to page of default data 
  					 ; group
	
  	
		mov	R2, [R0+]
	atomic	#4
	push	R2		; push segment number
	mov	R2, [R0+]
	push	R2		; push segment offset
	rets	
__C_INIT	ENDP
__C_INIT_PR	ENDS				
		REGDEF R0-R15			; Register usage

	
	NAME	CSTART		; module name.
	
PUBLIC RBANK

  
  
	EXTERN	_main:FAR		; start label user program.


	PUBLIC	__IDLE			; cstart end
	PUBLIC	__EXIT			; address to jump to on 'exit()'.



EXTERN __C_INIT:FAR
		

	; Value definitions for System Configuration Register : SYSCON

        ; XBUS Peripheral Share Mode Control (XPER-SHARE) bit. SYSCON.0
		; 0 = Disable external accesses to XBUS peripherals
				; 1 = XBUS peripherals accessible via 
				;     external bus during hold mode

	; Visible Mode Control (VISIBLE) bit. SYSCON.1
		; 0 = Accesses to XBUS peripherals internally
				; 1 = XBUS peripherals accessible visible on
                                ;     external pins

	; XBUS Peripheral (XPEN) Enable bit. SYSCON.2
				;     are done internally
				; 1 = On-chip X-Peripherals Enable

	; Bidirectional Reset (BDRSTEN) Enable bit. SYSCON.3
		; 0 = Pin RSTIN is input only
				; 1 = Pin RSTIN pulled low during internal
				;     reset after software or WDT reset

	; Oscillator Watchdog (OWDDIS) Disable bit. SYSCON.4
		; 0 = Enable on-chip oscillator watchdog
				; 1 = Disable on-chip oscillator watchdog

	; Chip Selected Configuration Control (CSCFG) bit. SYSCON.6
		; 0 = Latched CS mode
				; 1 = Unlatched CS mode

	; Write Configuration Mode Control Bit (CLKOUT) Enable bit. SYSCON.7
		; 0 = Normal operation of WR# abd BHE# (Reset)
				; 1 = WR# acts as WRL#, BHE# acts as WRH#

	; System Clock Output (CLKOUT) Enable bit. SYSCON.8
				; 1 = Enabled

	; Byte High Enable (BHE#) pin control bit. SYSCON.9
		; 0 = Enabled (Reset value)
				; 1 = Disabled

	; Internal ROM Access (ROMEN) Enable bit. SYSCON.10
				; Reset value determined by EA pin
				; 1 = Enable Internal ROM

	; Segmentation Disable control bit. SYSCON.11


	; ROM Segment Mapping control bit. SYSCON.12
		; 0 = Map internal ROM to segment 0 (Reset)
				; 1 = Map internal ROM to segment 1

	; Stack Size selection of between 32 and 512 words. SYSCON[15..13]
				; 1 = 128 words
				; 2 =  64 words
				; 3 =  32 words
				; 4 = 512 words
				; 7 = No wrapping

	; Process SYSCON low byte and high byte values.
	SYSC_L  	EQU	((00h<<7) | (00h<<6) | (01h<<4) | (00h<<3) | (0<<2) | (00h<<1) | 00h)
	SYSC_H  	EQU  	((0<<5) | (00h<<4) | (0<<3) | (0<<2) | (00h<<1) | 0)
	SYSC_M_L	EQU	0DFH	; Mask low byte SYSCON.
	SYSC_M_H	EQU	0FFH	; Mask high byte SYSCON.


	; Value definitions for System Configuration Register : SYSCON2

	; SYSCON Release Function (SYSRLS) field. SYSCON2[0..3]
				; Unlock sequence field after EINIT

	; Power Down Control (PDCON) field. SYSCON2[4..5]
		; 0 = RTC on, Ports on (Reset)
				; 1 = RTC on, Ports off
				; 2 = RTC off, Ports on
				; 3 = RTC off, Ports off

	; RTC Clock Source (RCS) bit. SYSCON2.6
			; 0 = Main oscillator
				; 1 = Reserved

	; SDD Clock Source (SCS) bit. SYSCON2.7
			; 0 = Main oscillator
				; 1 = Reserved

	; Clock State Control (CLKCON) field. SYSCON2[8..9]
		; 0 = Run on configured basic frequency
				; 1 = Run on slow down frequency, PLL ON
				; 2 = Run on slow down frequency, PLL OFF

	; Reload Counter Value for Slowdown Divider (CLKREL) field. SYSCON2[10..14]
		; Reload value


	; Clock Signal Status (CLKLOCK) bit is read only. SYSCON2.15

	; Process SYSCON2 low byte and high byte values.
	SYSC2_L  	EQU	((00h<<7) | (00h<<6) | ((00h&0003h)<<4))
	SYSC2_H  	EQU  	(((00h&001fh)<<2) | (00h&0003h))
	SYSC2_M_L	EQU	0F0H	; Mask low byte SYSCON2.
	SYSC2_M_H	EQU	07FH	; Mask high byte SYSCON2.


	; Value definitions for System Configuration Register : SYSCON3

	; Analog/Digital Converter (ADCDIS) enable bit. SYSCON3.0
		; 0 = Disable ADC convertor
				; 1 = Enable ADC convertor

	; USART ASC0 (ASC0DIS) enable bit. SYSCON3.1
		; 0 = Disable USART ASC0
				; 1 = Enable USART ASC0

	; Synchronous Serial Channel SSC (SSCDIS) enable bit. SYSCON3.2
		; 0 = Disable Synchronous Serial Channel SSC
				; 1 = Enable Synchronous Serial Channel SSC

	; General Purpose Timer Blocks (GPTDIS) enable bit. SYSCON3.3
  		; 0 = Disable General Purpose Timer Blocks
				; 1 = Enable General Purpose Timer Blocks
  

	
	; General Purpose Timer Block 2 (GPT2DIS) enable bit. SYSCON3.4
		; 0 = Disable General Purpose Timer Block 2
				; 1 = Enable General Purpose Timer Block 2

	; On-chip Flash Memory Module (FMDIS) enable bit. SYSCON3.5
		; 0 = Disable on-chip Flash Memory Module
				; 1 = Enable on-chip Flash Memory Module

	; CAPCOM Unit 1 (CC1DIS) enable bit. SYSCON3.6
		; 0 = Disable CAPCOM Unit 1
				; 1 = Enable CAPCOM Unit 1

	; CAPCOM Unit 2 (CC2DIS) enable bit. SYSCON3.7
		; 0 = Disable CAPCOM Unit 2
				; 1 = Enable CAPCOM Unit 2

	; CAPCOM Unit 6 (CC6DIS) enable bit. SYSCON3.8
		; 0 = Disable CAPCOM Unit 6
				; 1 = Enable CAPCOM Unit 6

	; USART ASC1 (ASC1DIS) enable bit. SYSCON3.10
		; 0 = Disable USART ASC1
				; 1 = Enable USART ASC1

	; On-chip I2C Bus Module (I2CDIS) enable bit. SYSCON3.11
		; 0 = Disable On-chip I2C Bus Module
				; 1 = Enable On-chip I2C Bus Module

	; On-chip CAN Module 1 (CAN1DIS) enable bit. SYSCON3.13
		; 0 = Disable On-chip CAN Module 1
				; 1 = Enable On-chip CAN Module 1

	; Peripheral Clock Driver (PCDDIS) enable bit. SYSCON3.15
		; 0 = Disable Peripheral Clock Driver
				; 1 = Enable Peripheral Clock Driver

	; Process SYSCON3 low byte and high byte values.
	SYSC3	  	EQU	((00h<<15) | (00h<<13) | (00h<<11) | (00h<<10) | (00h<<8) | (00h<<7) | (00h<<6) |(00h<<5) | (00h<<4) | (00h<<3) |(00h<<2) |(00h<<1) | 00h)

	; Value definitions for System Configuration Register : BUSCON0

	; Memory Cycle Time is extended by a number of additional State Times.
	; in a range from 0 through 15. BUSCON0[3..0]
				; Reset value MCTC = 15 additional state times

				; 0 = Memory wait states is 0 (MCTC = 0FH).

	; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON0.4
		; 1 = No Delay Time
				; 0 = Delay Time (Reset value)

	; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON0.5
				; 1 = No Delay Time

	; External bus configurations. BUSCON0[7..6]
					; After reset determined by the state 
					; of the port pins P0L.7 and P0L.6.
					
	; ALE Signal is lengthened by either 1 or 0 State Times. BUSCON0.9
	; Do not disable the ALE lengthening option for a multiplexed bus
	; configuration. See problem 17 in errata sheet SAB-C167A-LM,ES-AC,1.1
	; on page 4/9.



	; Bus Active (BUSACT0) control bit. BUSCON0.10
				; 1 = Enable external bus
	
	; READY# Input Enable control bit. BUSCON0.12
				; 1 = Enabled

	; Read Chip Select (CSREN0) enable bit. BUSCON0.14
				; 1 = Chip select for duration of read command

	; Write Chip Select (CSWEN0) enable bit. BUSCON0.15
				; 1 = Chip select for duration of write command

	; Process BUSCON0 low byte and high byte values
	BUSC0_L		EQU	((0<<5) | (01h<<4) | ((~1)&000Fh))
	BUSC0_H		EQU	((0<<7) | (0<<6) | (0<<4) | (1<<2) | (0<<1))
	BUSC0_M_L	EQU	03Fh	; Mask low byte BUSCON0
	BUSC0_M_H	EQU	0D6h	; Mask high byte BUSCON0

	; Value definitions for System Configuration Register : BUSCON1

	; Memory Cycle Time is extended by a number of additional State Times.
	; in a range from 0 through 15. BUSCON1[3..0]
				; Reset value MCTC = 15 additional state times

		; 1 = Memory wait states is 1 (MCTC = 0EH).
				; 0 = Memory wait states is 0 (MCTC = 0FH).

	; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON1.4
		; 1 = No Delay Time
				; 0 = Delay Time (Reset value)

	; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON1.5
		; 0 = Delay Time (Reset value)
				; 1 = No Delay Time

	; External bus configurations. BUSCON1[7..6]
		; 0 = 8-bit Demultiplexed Bus
				; 1 = 8-bit Multiplexed Bus
				; 2 = 16-bit Demultiplexed Bus
				; 3 = 16-bit Multiplexed Bus

	; ALE Signal is lengthened by either 1 or 0 State Times. BUSCON1.9

		; 0 = No Delay (Reset value if EA# pin is high
				; 1 = Delay (Reset value if EA# pin is high

	; Bus Active (BUSACT1) control bit. BUSCON1.10
				; 1 = Enable external bus
	
	; READY# Input Enable control bit. BUSCON1.12
		; 0 = Disabled (Reset value)
				; 1 = Enabled

	; Read Chip Select (CSREN1) enable bit. BUSCON1.14
		; 0 = Chip select independend of read command
				; 1 = Chip select for duration of read command

	; Write Chip Select (CSWEN1) enable bit. BUSCON1.15
		; 0 = Chip select independend of write command
				; 1 = Chip select for duration of write command

	; Process BUSCON1 low byte and high byte values
	BUSC1		EQU	((00h<<15) | (00h<<14) | (00h<<12) | (0<<10) | (00h<<9) | (01h<<6) | (00h<<5) | (01h<<4) | ((~01h)&000Fh))

	; Value definitions for System Configuration Register : BUSCON2

	; Memory Cycle Time is extended by a number of additional State Times.
	; in a range from 0 through 15. BUSCON2[3..0]
				; Reset value MCTC = 15 additional state times

		; 1 = Memory wait states is 1 (MCTC = 0EH).
				; 0 = Memory wait states is 0 (MCTC = 0FH).

	; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON2.4
		; 1 = No Delay Time
				; 0 = Delay Time (Reset value)