start.lst

uc/os在c167上的移植代码

                   541   
                   542           
                   543           ; General Purpose Timer Block 2 (GPT2DIS) enable bit. SYSCON3.4
                   544                   ; 0 = Disable General Purpose Timer Block 2
                   545                                   ; 1 = Enable General Purpose Timer Block 2
                   546   
                   547           ; On-chip Flash Memory Module (FMDIS) enable bit. SYSCON3.5
                   548                   ; 0 = Disable on-chip Flash Memory Module
                   549                                   ; 1 = Enable on-chip Flash Memory Module
C166/ST10 assembler v6.0 r2 SN00082920-083 (c) 1998 TASKING, Inc.                       Date: Dec  5 2000  Time: 10:02:43  Page:  11
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 LOC CODE        LINE   SOURCELINE

                   550   
                   551           ; CAPCOM Unit 1 (CC1DIS) enable bit. SYSCON3.6
                   552                   ; 0 = Disable CAPCOM Unit 1
                   553                                   ; 1 = Enable CAPCOM Unit 1
                   554   
                   555           ; CAPCOM Unit 2 (CC2DIS) enable bit. SYSCON3.7
                   556                   ; 0 = Disable CAPCOM Unit 2
                   557                                   ; 1 = Enable CAPCOM Unit 2
                   558   
                   559           ; CAPCOM Unit 6 (CC6DIS) enable bit. SYSCON3.8
                   560                   ; 0 = Disable CAPCOM Unit 6
                   561                                   ; 1 = Enable CAPCOM Unit 6
                   562   
                   563           ; USART ASC1 (ASC1DIS) enable bit. SYSCON3.10
                   564                   ; 0 = Disable USART ASC1
                   565                                   ; 1 = Enable USART ASC1
                   566   
                   567           ; On-chip I2C Bus Module (I2CDIS) enable bit. SYSCON3.11
                   568                   ; 0 = Disable On-chip I2C Bus Module
                   569                                   ; 1 = Enable On-chip I2C Bus Module
                   570   
                   571           ; On-chip CAN Module 1 (CAN1DIS) enable bit. SYSCON3.13
                   572                   ; 0 = Disable On-chip CAN Module 1
                   573                                   ; 1 = Enable On-chip CAN Module 1
                   574   
                   575           ; Peripheral Clock Driver (PCDDIS) enable bit. SYSCON3.15
                   576                   ; 0 = Disable Peripheral Clock Driver
                   577                                   ; 1 = Enable Peripheral Clock Driver
                   578   
                   579           ; Process SYSCON3 low byte and high byte values.
                   580           SYSC3           EQU     ((00h<<15) | (00h<<13) | (00h<<11) | (00h<<10) | (00h<<8) | (00h<<7) | (00h
                         <<6) |(00h<<5) | (00h<<4) | (00h<<3) |(00h<<2) |(00h<<1) | 00h)
                   581   
                   582           ; Value definitions for System Configuration Register : BUSCON0
                   583   
                   584           ; Memory Cycle Time is extended by a number of additional State Times.
                   585           ; in a range from 0 through 15. BUSCON0[3..0]
                   586                                   ; Reset value MCTC = 15 additional state times
                   587   
                   588                                   ; 0 = Memory wait states is 0 (MCTC = 0FH).
                   589   
                   590           ; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON0.4
                   591                   ; 1 = No Delay Time
                   592                                   ; 0 = Delay Time (Reset value)
                   593   
                   594           ; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON0.5
                   595                                   ; 1 = No Delay Time
                   596   
                   597           ; External bus configurations. BUSCON0[7..6]
                   598                                           ; After reset determined by the state 
                   599                                           ; of the port pins P0L.7 and P0L.6.
                   600                                           
                   601           ; ALE Signal is lengthened by either 1 or 0 State Times. BUSCON0.9
                   602           ; Do not disable the ALE lengthening option for a multiplexed bus
                   603           ; configuration. See problem 17 in errata sheet SAB-C167A-LM,ES-AC,1.1
C166/ST10 assembler v6.0 r2 SN00082920-083 (c) 1998 TASKING, Inc.                       Date: Dec  5 2000  Time: 10:02:43  Page:  12
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 LOC CODE        LINE   SOURCELINE

                   604           ; on page 4/9.
                   605   
                   606   
                   607   
                   608           ; Bus Active (BUSACT0) control bit. BUSCON0.10
                   609                                   ; 1 = Enable external bus
                   610           
                   611           ; READY# Input Enable control bit. BUSCON0.12
                   612                                   ; 1 = Enabled
                   613   
                   614           ; Read Chip Select (CSREN0) enable bit. BUSCON0.14
                   615                                   ; 1 = Chip select for duration of read command
                   616   
                   617           ; Write Chip Select (CSWEN0) enable bit. BUSCON0.15
                   618                                   ; 1 = Chip select for duration of write command
                   619   
                   620           ; Process BUSCON0 low byte and high byte values
                   621           BUSC0_L         EQU     ((0<<5) | (01h<<4) | ((~1)&000Fh))
                   622           BUSC0_H         EQU     ((0<<7) | (0<<6) | (0<<4) | (1<<2) | (0<<1))
                   623           BUSC0_M_L       EQU     03Fh    ; Mask low byte BUSCON0
                   624           BUSC0_M_H       EQU     0D6h    ; Mask high byte BUSCON0
                   625   
                   626           ; Value definitions for System Configuration Register : BUSCON1
                   627   
                   628           ; Memory Cycle Time is extended by a number of additional State Times.
                   629           ; in a range from 0 through 15. BUSCON1[3..0]
                   630                                   ; Reset value MCTC = 15 additional state times
                   631   
                   632                   ; 1 = Memory wait states is 1 (MCTC = 0EH).
                   633                                   ; 0 = Memory wait states is 0 (MCTC = 0FH).
                   634   
                   635           ; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON1.4
                   636                   ; 1 = No Delay Time
                   637                                   ; 0 = Delay Time (Reset value)
                   638   
                   639           ; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON1.5
                   640                   ; 0 = Delay Time (Reset value)
                   641                                   ; 1 = No Delay Time
                   642   
                   643           ; External bus configurations. BUSCON1[7..6]
                   644                   ; 0 = 8-bit Demultiplexed Bus
                   645                                   ; 1 = 8-bit Multiplexed Bus
                   646                                   ; 2 = 16-bit Demultiplexed Bus
                   647                                   ; 3 = 16-bit Multiplexed Bus
                   648   
                   649           ; ALE Signal is lengthened by either 1 or 0 State Times. BUSCON1.9
                   650   
                   651                   ; 0 = No Delay (Reset value if EA# pin is high
                   652                                   ; 1 = Delay (Reset value if EA# pin is high
                   653   
                   654           ; Bus Active (BUSACT1) control bit. BUSCON1.10
                   655                                   ; 1 = Enable external bus
                   656           
                   657           ; READY# Input Enable control bit. BUSCON1.12
                   658                   ; 0 = Disabled (Reset value)
C166/ST10 assembler v6.0 r2 SN00082920-083 (c) 1998 TASKING, Inc.                       Date: Dec  5 2000  Time: 10:02:43  Page:  13
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 LOC CODE        LINE   SOURCELINE

                   659                                   ; 1 = Enabled
                   660   
                   661           ; Read Chip Select (CSREN1) enable bit. BUSCON1.14
                   662                   ; 0 = Chip select independend of read command
                   663                                   ; 1 = Chip select for duration of read command
                   664   
                   665           ; Write Chip Select (CSWEN1) enable bit. BUSCON1.15
                   666                   ; 0 = Chip select independend of write command
                   667                                   ; 1 = Chip select for duration of write command
                   668   
                   669           ; Process BUSCON1 low byte and high byte values
                   670           BUSC1           EQU     ((00h<<15) | (00h<<14) | (00h<<12) | (0<<10) | (00h<<9) | (01h<<6) | (00h<<
                         5) | (01h<<4) | ((~01h)&000Fh))
                   671   
                   672           ; Value definitions for System Configuration Register : BUSCON2
                   673   
                   674           ; Memory Cycle Time is extended by a number of additional State Times.
                   675           ; in a range from 0 through 15. BUSCON2[3..0]
                   676                                   ; Reset value MCTC = 15 additional state times
                   677   
                   678                   ; 1 = Memory wait states is 1 (MCTC = 0EH).
                   679                                   ; 0 = Memory wait states is 0 (MCTC = 0FH).
                   680   
                   681           ; The Read/Write Signal Delay is 0.5 or 0 State Times. BUSCON2.4
                   682                   ; 1 = No Delay Time
                   683                                   ; 0 = Delay Time (Reset value)
                   684   
                   685           ; Memory Tri-state is extended by either 1 or 0 State Times. BUSCON2.5
                   686                   ; 0 = Delay Time (Reset value)
                   687                                   ; 1 = No Delay Time
                   688   
                   689           ; External bus configurations. BUSCON2[7..6]
                   690                   ; 0 = 8-bit Demultiplexed Bus
                   691                                   ; 1 = 8-bit Multiplexed Bus
                   692                                   ; 2 = 16-bit Demultiplexed Bus
                   693                                   ; 3 = 16-bit Multiplexed Bus
                   694   
                   695           ; External bus configurations. BUSCON2[7..6]
                   696                                           ; After reset determined by the state 
                   697                                           ; of the port pins P0L.7 and P0L.6.
                   698                                           
                   699           ; ALE Signal is lengthened by either 1 or 0 State Times. BUSCON2.9
                   700   
                   701                   ; 0 = No Delay (Reset value if EA# pin is high
                   702                                   ; 1 = Delay (Reset value if EA# pin is high
                   703   
                   704           ; Bus Active (BUSACT2) control bit. BUSCON2.10
                   705                                   ; 1 = Enable external bus
                   706           
                   707           ; READY# Input Enable control bit. BUSCON2.12
                   708                   ; 0 = Disabled (Reset value)
                   709                                   ; 1 = Enabled
                   710   
                   711           ; Read Chip Select (CSREN2) enable bit. BUSCON2.14
                   712                   ; 0 = Chip select independend of read command
C166/ST10 assembler v6.0 r2 SN00082920-083 (c) 1998 TASKING, Inc.                       Date: Dec  5 2000  Time: 10:02:43  Page:  14
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 LOC CODE        LINE   SOURCELINE

                   713                                   ; 1 = Chip select for duration of read command
                   714   
                   715           ; Write Chip Select (CSWEN2) enable bit. BUSCON2.15