📄 start.lst
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359 ; segmented with DPP usage linear or
360 ; paged.)
00F2 9814 361 MOV POF_RAM, [R4+] ; move intra-page offset address ram
362 ; data block to POF_RAM=R1
00F4 1AF140C0 363 BFLDH SOF_RAM, #0C0H, #040H ; DPP1:POF_RAM ->SOF_RAM=R1
00F8 940402FE 364 MOV DPP1, [R4] ; load data page pointer register DPP1
365 ; with data page of ram data block
00FC 0842 366 ADD R4, #2 ; inc offset address to ram data section
367 ; C166_BSS and also insure a delay for
368 ; pipeline effect. (DPP1 set)
369 ;
00FE 9854 370 MOV R5, [R4+] ; number of bytes to clear in specified
371 ; ram data block
372 ;
0100 A005 373 CB06_1: CMPD1 R5, #0 ; test on data block end
0102 2DD8 374 JMP CC_EQ, BSS ; if( block end ) next initialization
375
0104 A4011CFF 376 MOVB [SOF_RAM], ZEROS ; clear byte
0108 0811 377 ADD SOF_RAM, #1 ; inc SOF_RAM
010A 0DFA 378 JMP CC_UC, CB06_1 ; jump for next byte clear
379
380
381
382
010C 383 BSS_END:
384
C166/ST10 assembler v6.0 r2 SN00082920-083 (c) 1998 TASKING, Inc. Date: Dec 5 2000 Time: 10:02:43 Page: 8
start
LOC CODE LINE SOURCELINE
385
386
010C E6000000 387 MOV DPP0, #0 ; restore DPP0 to its default value
0110 E6010000 R 388 MOV DPP1, #PAG ?USRSTACK_TOP ; set DPP1 to page of user stack
0114 E6020000 R 389 MOV DPP2, #PAG C166_DGROUP ; set DPP2 to page of default data
390 ; group
391
392
0118 9820 393 mov R2, [R0+]
011A D130 394 atomic #4
011C ECF2 4 395 push R2 ; push segment number
011E 9820 3 396 mov R2, [R0+]
0120 ECF2 2 397 push R2 ; push segment offset
0122 DB00 1 398 rets
399 __C_INIT ENDP
400 __C_INIT_PR ENDS
401 REGDEF R0-R15 ; Register usage
402
403
404 NAME CSTART ; module name.
405
406 PUBLIC RBANK
407
408
409
410 EXTERN _main:FAR ; start label user program.
411
412
413 PUBLIC __IDLE ; cstart end
414 PUBLIC __EXIT ; address to jump to on 'exit()'.
415
416
417
418 EXTERN __C_INIT:FAR
419
420
421 ; Value definitions for System Configuration Register : SYSCON
422
423 ; XBUS Peripheral Share Mode Control (XPER-SHARE) bit. SYSCON.0
424 ; 0 = Disable external accesses to XBUS peripherals
425 ; 1 = XBUS peripherals accessible via
426 ; external bus during hold mode
427
428 ; Visible Mode Control (VISIBLE) bit. SYSCON.1
429 ; 0 = Accesses to XBUS peripherals internally
430 ; 1 = XBUS peripherals accessible visible on
431 ; external pins
432
433 ; XBUS Peripheral (XPEN) Enable bit. SYSCON.2
434 ; are done internally
435 ; 1 = On-chip X-Peripherals Enable
436
437 ; Bidirectional Reset (BDRSTEN) Enable bit. SYSCON.3
438 ; 0 = Pin RSTIN is input only
439 ; 1 = Pin RSTIN pulled low during internal
C166/ST10 assembler v6.0 r2 SN00082920-083 (c) 1998 TASKING, Inc. Date: Dec 5 2000 Time: 10:02:43 Page: 9
start
LOC CODE LINE SOURCELINE
440 ; reset after software or WDT reset
441
442 ; Oscillator Watchdog (OWDDIS) Disable bit. SYSCON.4
443 ; 0 = Enable on-chip oscillator watchdog
444 ; 1 = Disable on-chip oscillator watchdog
445
446 ; Chip Selected Configuration Control (CSCFG) bit. SYSCON.6
447 ; 0 = Latched CS mode
448 ; 1 = Unlatched CS mode
449
450 ; Write Configuration Mode Control Bit (CLKOUT) Enable bit. SYSCON.7
451 ; 0 = Normal operation of WR# abd BHE# (Reset)
452 ; 1 = WR# acts as WRL#, BHE# acts as WRH#
453
454 ; System Clock Output (CLKOUT) Enable bit. SYSCON.8
455 ; 1 = Enabled
456
457 ; Byte High Enable (BHE#) pin control bit. SYSCON.9
458 ; 0 = Enabled (Reset value)
459 ; 1 = Disabled
460
461 ; Internal ROM Access (ROMEN) Enable bit. SYSCON.10
462 ; Reset value determined by EA pin
463 ; 1 = Enable Internal ROM
464
465 ; Segmentation Disable control bit. SYSCON.11
466
467
468 ; ROM Segment Mapping control bit. SYSCON.12
469 ; 0 = Map internal ROM to segment 0 (Reset)
470 ; 1 = Map internal ROM to segment 1
471
472 ; Stack Size selection of between 32 and 512 words. SYSCON[15..13]
473 ; 1 = 128 words
474 ; 2 = 64 words
475 ; 3 = 32 words
476 ; 4 = 512 words
477 ; 7 = No wrapping
478
479 ; Process SYSCON low byte and high byte values.
480 SYSC_L EQU ((00h<<7) | (00h<<6) | (01h<<4) | (00h<<3) | (0<<2) | (00h<<1) | 00h)
481 SYSC_H EQU ((0<<5) | (00h<<4) | (0<<3) | (0<<2) | (00h<<1) | 0)
482 SYSC_M_L EQU 0DFH ; Mask low byte SYSCON.
483 SYSC_M_H EQU 0FFH ; Mask high byte SYSCON.
484
485
486 ; Value definitions for System Configuration Register : SYSCON2
487
488 ; SYSCON Release Function (SYSRLS) field. SYSCON2[0..3]
489 ; Unlock sequence field after EINIT
490
491 ; Power Down Control (PDCON) field. SYSCON2[4..5]
492 ; 0 = RTC on, Ports on (Reset)
493 ; 1 = RTC on, Ports off
494 ; 2 = RTC off, Ports on
C166/ST10 assembler v6.0 r2 SN00082920-083 (c) 1998 TASKING, Inc. Date: Dec 5 2000 Time: 10:02:43 Page: 10
start
LOC CODE LINE SOURCELINE
495 ; 3 = RTC off, Ports off
496
497 ; RTC Clock Source (RCS) bit. SYSCON2.6
498 ; 0 = Main oscillator
499 ; 1 = Reserved
500
501 ; SDD Clock Source (SCS) bit. SYSCON2.7
502 ; 0 = Main oscillator
503 ; 1 = Reserved
504
505 ; Clock State Control (CLKCON) field. SYSCON2[8..9]
506 ; 0 = Run on configured basic frequency
507 ; 1 = Run on slow down frequency, PLL ON
508 ; 2 = Run on slow down frequency, PLL OFF
509
510 ; Reload Counter Value for Slowdown Divider (CLKREL) field. SYSCON2[10..14]
511 ; Reload value
512
513
514 ; Clock Signal Status (CLKLOCK) bit is read only. SYSCON2.15
515
516 ; Process SYSCON2 low byte and high byte values.
517 SYSC2_L EQU ((00h<<7) | (00h<<6) | ((00h&0003h)<<4))
518 SYSC2_H EQU (((00h&001fh)<<2) | (00h&0003h))
519 SYSC2_M_L EQU 0F0H ; Mask low byte SYSCON2.
520 SYSC2_M_H EQU 07FH ; Mask high byte SYSCON2.
521
522
523 ; Value definitions for System Configuration Register : SYSCON3
524
525 ; Analog/Digital Converter (ADCDIS) enable bit. SYSCON3.0
526 ; 0 = Disable ADC convertor
527 ; 1 = Enable ADC convertor
528
529 ; USART ASC0 (ASC0DIS) enable bit. SYSCON3.1
530 ; 0 = Disable USART ASC0
531 ; 1 = Enable USART ASC0
532
533 ; Synchronous Serial Channel SSC (SSCDIS) enable bit. SYSCON3.2
534 ; 0 = Disable Synchronous Serial Channel SSC
535 ; 1 = Enable Synchronous Serial Channel SSC
536
537 ; General Purpose Timer Blocks (GPTDIS) enable bit. SYSCON3.3
538 ; 0 = Disable General Purpose Timer Blocks
539 ; 1 = Enable General Purpose Timer Blocks
540
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